4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
35 uses MAINBOARD_PART_NUMBER
37 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
44 uses DEFAULT_CONSOLE_LOGLEVEL
45 uses MAXIMUM_CONSOLE_LOGLEVEL
46 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
56 uses CONFIG_CONSOLE_VGA
57 uses CONFIG_PCI_ROM_RUN
58 uses HW_MEM_HOLE_SIZEK
64 uses CONFIG_USE_PRINTK_IN_CAR
66 uses ENABLE_APIC_EXT_ID
75 ## ROM_SIZE is the size of boot ROM that this board will use.
77 default ROM_SIZE=524288
80 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
82 #default FALLBACK_SIZE=131072
84 default FALLBACK_SIZE=0x40000
87 ## Build code for the fallback boot
89 default HAVE_FALLBACK_BOOT=1
92 ## Build code to reset the motherboard from coreboot
94 default HAVE_HARD_RESET=1
97 ## Build code to export a programmable irq routing table
99 default HAVE_PIRQ_TABLE=1
100 default IRQ_SLOT_COUNT=22
103 ## Build code to export an x86 MP table
104 ## Useful for specifying IRQ routing values
106 default HAVE_MP_TABLE=1
109 ## Build code to export a CMOS option table
111 default HAVE_OPTION_TABLE=1
114 ## Move the default coreboot cmos range off of AMD RTC registers
116 default LB_CKS_RANGE_START=49
117 default LB_CKS_RANGE_END=122
118 default LB_CKS_LOC=123
121 ## Build code for SMP support
122 ## Only worry about 2 micro processors
125 default CONFIG_MAX_CPUS=8
126 default CONFIG_MAX_PHYSICAL_CPUS=4
127 default CONFIG_LOGICAL_CPUS=1
130 default CONFIG_CHIP_NAME=1
133 default HW_MEM_HOLE_SIZEK=0x100000
136 default CONFIG_CONSOLE_VGA=1
137 default CONFIG_PCI_ROM_RUN=1
141 ## enable CACHE_AS_RAM specifics
143 default USE_DCACHE_RAM=1
144 default DCACHE_RAM_BASE=0xcf000
145 default DCACHE_RAM_SIZE=0x1000
146 default CONFIG_USE_INIT=0
148 default ENABLE_APIC_EXT_ID=1
149 default APIC_ID_OFFSET=0x10
150 default LIFT_BSP_APIC_ID=0
154 ## Build code to setup a generic IOAPIC
156 default CONFIG_IOAPIC=1
159 ## Clean up the motherboard id strings
161 default MAINBOARD_VENDOR="Tyan"
162 default MAINBOARD_PART_NUMBER="s4880"
163 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
164 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
167 ### coreboot layout values
170 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
171 default ROM_IMAGE_SIZE = 65536
174 ## Use a small 8K stack
176 default STACK_SIZE=0x2000
179 ## Use a small 16K heap
181 default HEAP_SIZE=0x4000
184 ## Only use the option table in a normal image
186 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
189 ## Coreboot C code runs at this location in RAM
191 default _RAMBASE=0x00004000
194 ## Load the payload from the ROM
196 default CONFIG_ROM_PAYLOAD = 1
199 ### Defaults of options that you may want to override in the target config file
203 ## The default compiler
205 default CC="$(CROSS_COMPILE)gcc -m32"
209 ## Disable the gdb stub by default
211 default CONFIG_GDB_STUB=0
213 default CONFIG_USE_PRINTK_IN_CAR=1
216 ## The Serial Console
219 # To Enable the Serial Console
220 default CONFIG_CONSOLE_SERIAL8250=1
222 ## Select the serial console baud rate
223 default TTYS0_BAUD=115200
224 #default TTYS0_BAUD=57600
225 #default TTYS0_BAUD=38400
226 #default TTYS0_BAUD=19200
227 #default TTYS0_BAUD=9600
228 #default TTYS0_BAUD=4800
229 #default TTYS0_BAUD=2400
230 #default TTYS0_BAUD=1200
232 # Select the serial console base port
233 default TTYS0_BASE=0x3f8
235 # Select the serial protocol
236 # This defaults to 8 data bits, 1 stop bit, and no parity
237 default TTYS0_LCS=0x3
240 ### Select the coreboot loglevel
242 ## EMERG 1 system is unusable
243 ## ALERT 2 action must be taken immediately
244 ## CRIT 3 critical conditions
245 ## ERR 4 error conditions
246 ## WARNING 5 warning conditions
247 ## NOTICE 6 normal but significant condition
248 ## INFO 7 informational
249 ## DEBUG 8 debug-level messages
250 ## SPEW 9 Way too many details
252 ## Request this level of debugging output
253 default DEFAULT_CONSOLE_LOGLEVEL=8
254 ## At a maximum only compile in this level of debugging
255 default MAXIMUM_CONSOLE_LOGLEVEL=8
258 ## Select power on after power fail setting
259 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
266 default CONFIG_ROMFS=0