1 uses CONFIG_HAVE_MP_TABLE
3 uses CONFIG_HAVE_PIRQ_TABLE
4 uses CONFIG_USE_FALLBACK_IMAGE
5 uses CONFIG_HAVE_FALLBACK_BOOT
6 uses CONFIG_HAVE_HARD_RESET
7 uses CONFIG_IRQ_SLOT_COUNT
8 uses CONFIG_HAVE_OPTION_TABLE
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
14 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_ROM_SECTION_SIZE
17 uses CONFIG_ROM_IMAGE_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
24 uses CONFIG_PAYLOAD_SIZE
26 uses CONFIG_XIP_ROM_SIZE
27 uses CONFIG_XIP_ROM_BASE
28 uses CONFIG_STACK_SIZE
30 uses CONFIG_USE_OPTION_TABLE
31 uses CONFIG_LB_CKS_RANGE_START
32 uses CONFIG_LB_CKS_RANGE_END
33 uses CONFIG_LB_CKS_LOC
35 uses CONFIG_MAINBOARD_PART_NUMBER
36 uses CONFIG_MAINBOARD_VENDOR
37 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
38 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
39 uses COREBOOT_EXTRA_VERSION
41 uses CONFIG_TTYS0_BAUD
42 uses CONFIG_TTYS0_BASE
44 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
45 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
46 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
47 uses CONFIG_CONSOLE_SERIAL8250
48 uses CONFIG_HAVE_INIT_TIMER
51 uses CONFIG_CROSS_COMPILE
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses CONFIG_HW_MEM_HOLE_SIZEK
59 uses CONFIG_USE_DCACHE_RAM
60 uses CONFIG_DCACHE_RAM_BASE
61 uses CONFIG_DCACHE_RAM_SIZE
63 uses CONFIG_USE_PRINTK_IN_CAR
65 uses CONFIG_ENABLE_APIC_EXT_ID
66 uses CONFIG_APIC_ID_OFFSET
67 uses CONFIG_LIFT_BSP_APIC_ID
74 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
76 default CONFIG_ROM_SIZE=524288
79 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
81 #default CONFIG_FALLBACK_SIZE=131072
83 default CONFIG_FALLBACK_SIZE=0x40000
86 ## Build code for the fallback boot
88 default CONFIG_HAVE_FALLBACK_BOOT=1
91 ## Build code to reset the motherboard from coreboot
93 default CONFIG_HAVE_HARD_RESET=1
96 ## Build code to export a programmable irq routing table
98 default CONFIG_HAVE_PIRQ_TABLE=1
99 default CONFIG_IRQ_SLOT_COUNT=22
102 ## Build code to export an x86 MP table
103 ## Useful for specifying IRQ routing values
105 default CONFIG_HAVE_MP_TABLE=1
108 ## Build code to export a CMOS option table
110 default CONFIG_HAVE_OPTION_TABLE=1
113 ## Move the default coreboot cmos range off of AMD RTC registers
115 default CONFIG_LB_CKS_RANGE_START=49
116 default CONFIG_LB_CKS_RANGE_END=122
117 default CONFIG_LB_CKS_LOC=123
120 ## Build code for SMP support
121 ## Only worry about 2 micro processors
124 default CONFIG_MAX_CPUS=8
125 default CONFIG_MAX_PHYSICAL_CPUS=4
126 default CONFIG_LOGICAL_CPUS=1
129 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
132 default CONFIG_CONSOLE_VGA=1
133 default CONFIG_PCI_ROM_RUN=1
137 ## enable CACHE_AS_RAM specifics
139 default CONFIG_USE_DCACHE_RAM=1
140 default CONFIG_DCACHE_RAM_BASE=0xcf000
141 default CONFIG_DCACHE_RAM_SIZE=0x1000
142 default CONFIG_USE_INIT=0
144 default CONFIG_ENABLE_APIC_EXT_ID=1
145 default CONFIG_APIC_ID_OFFSET=0x10
146 default CONFIG_LIFT_BSP_APIC_ID=0
150 ## Build code to setup a generic IOAPIC
152 default CONFIG_IOAPIC=1
155 ## Clean up the motherboard id strings
157 default CONFIG_MAINBOARD_VENDOR="Tyan"
158 default CONFIG_MAINBOARD_PART_NUMBER="s4880"
159 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
160 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
163 ### coreboot layout values
166 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
167 default CONFIG_ROM_IMAGE_SIZE = 65536
170 ## Use a small 8K stack
172 default CONFIG_STACK_SIZE=0x2000
175 ## Use a small 16K heap
177 default CONFIG_HEAP_SIZE=0x4000
180 ## Only use the option table in a normal image
182 default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
185 ## Coreboot C code runs at this location in RAM
187 default CONFIG_RAMBASE=0x00004000
190 ## Load the payload from the ROM
192 default CONFIG_ROM_PAYLOAD = 1
195 ### Defaults of options that you may want to override in the target config file
199 ## The default compiler
201 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
205 ## Disable the gdb stub by default
207 default CONFIG_GDB_STUB=0
209 default CONFIG_USE_PRINTK_IN_CAR=1
212 ## The Serial Console
215 # To Enable the Serial Console
216 default CONFIG_CONSOLE_SERIAL8250=1
218 ## Select the serial console baud rate
219 default CONFIG_TTYS0_BAUD=115200
220 #default CONFIG_TTYS0_BAUD=57600
221 #default CONFIG_TTYS0_BAUD=38400
222 #default CONFIG_TTYS0_BAUD=19200
223 #default CONFIG_TTYS0_BAUD=9600
224 #default CONFIG_TTYS0_BAUD=4800
225 #default CONFIG_TTYS0_BAUD=2400
226 #default CONFIG_TTYS0_BAUD=1200
228 # Select the serial console base port
229 default CONFIG_TTYS0_BASE=0x3f8
231 # Select the serial protocol
232 # This defaults to 8 data bits, 1 stop bit, and no parity
233 default CONFIG_TTYS0_LCS=0x3
236 ### Select the coreboot loglevel
238 ## EMERG 1 system is unusable
239 ## ALERT 2 action must be taken immediately
240 ## CRIT 3 critical conditions
241 ## ERR 4 error conditions
242 ## WARNING 5 warning conditions
243 ## NOTICE 6 normal but significant condition
244 ## INFO 7 informational
245 ## CONFIG_DEBUG 8 debug-level messages
246 ## SPEW 9 Way too many details
248 ## Request this level of debugging output
249 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
250 ## At a maximum only compile in this level of debugging
251 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
254 ## Select power on after power fail setting
255 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
262 default CONFIG_CBFS=0