3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
30 uses LB_CKS_RANGE_START
34 uses MAINBOARD_PART_NUMBER
36 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
37 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
38 uses COREBOOT_EXTRA_VERSION
43 uses DEFAULT_CONSOLE_LOGLEVEL
44 uses MAXIMUM_CONSOLE_LOGLEVEL
45 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
46 uses CONFIG_CONSOLE_SERIAL8250
55 uses CONFIG_CONSOLE_VGA
56 uses CONFIG_PCI_ROM_RUN
57 uses HW_MEM_HOLE_SIZEK
64 uses ENABLE_APIC_EXT_ID
73 ## ROM_SIZE is the size of boot ROM that this board will use.
75 default ROM_SIZE=524288
78 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
80 #default FALLBACK_SIZE=131072
82 default FALLBACK_SIZE=0x40000
85 ## Build code for the fallback boot
87 default HAVE_FALLBACK_BOOT=1
90 ## Build code to reset the motherboard from coreboot
92 default HAVE_HARD_RESET=1
95 ## Build code to export a programmable irq routing table
97 default HAVE_PIRQ_TABLE=1
98 default IRQ_SLOT_COUNT=22
101 ## Build code to export an x86 MP table
102 ## Useful for specifying IRQ routing values
104 default HAVE_MP_TABLE=1
107 ## Build code to export a CMOS option table
109 default HAVE_OPTION_TABLE=1
112 ## Move the default coreboot cmos range off of AMD RTC registers
114 default LB_CKS_RANGE_START=49
115 default LB_CKS_RANGE_END=122
116 default LB_CKS_LOC=123
119 ## Build code for SMP support
120 ## Only worry about 2 micro processors
123 default CONFIG_MAX_CPUS=8
124 default CONFIG_MAX_PHYSICAL_CPUS=4
125 default CONFIG_LOGICAL_CPUS=1
128 default CONFIG_CHIP_NAME=1
131 default HW_MEM_HOLE_SIZEK=0x100000
134 default CONFIG_CONSOLE_VGA=1
135 default CONFIG_PCI_ROM_RUN=1
139 ## enable CACHE_AS_RAM specifics
141 default USE_DCACHE_RAM=1
142 default DCACHE_RAM_BASE=0xcf000
143 default DCACHE_RAM_SIZE=0x1000
144 default CONFIG_USE_INIT=0
146 default ENABLE_APIC_EXT_ID=1
147 default APIC_ID_OFFSET=0x10
148 default LIFT_BSP_APIC_ID=0
152 ## Build code to setup a generic IOAPIC
154 default CONFIG_IOAPIC=1
157 ## Clean up the motherboard id strings
159 default MAINBOARD_VENDOR="Tyan"
160 default MAINBOARD_PART_NUMBER="s4880"
161 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
162 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x4880
165 ### coreboot layout values
168 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
169 default ROM_IMAGE_SIZE = 65536
172 ## Use a small 8K stack
174 default STACK_SIZE=0x2000
177 ## Use a small 16K heap
179 default HEAP_SIZE=0x4000
182 ## Only use the option table in a normal image
184 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
187 ## Coreboot C code runs at this location in RAM
189 default _RAMBASE=0x00004000
192 ## Load the payload from the ROM
194 default CONFIG_ROM_PAYLOAD = 1
197 ### Defaults of options that you may want to override in the target config file
201 ## The default compiler
203 default CC="$(CROSS_COMPILE)gcc -m32"
207 ## Disable the gdb stub by default
209 default CONFIG_GDB_STUB=0
212 ## The Serial Console
215 # To Enable the Serial Console
216 default CONFIG_CONSOLE_SERIAL8250=1
218 ## Select the serial console baud rate
219 default TTYS0_BAUD=115200
220 #default TTYS0_BAUD=57600
221 #default TTYS0_BAUD=38400
222 #default TTYS0_BAUD=19200
223 #default TTYS0_BAUD=9600
224 #default TTYS0_BAUD=4800
225 #default TTYS0_BAUD=2400
226 #default TTYS0_BAUD=1200
228 # Select the serial console base port
229 default TTYS0_BASE=0x3f8
231 # Select the serial protocol
232 # This defaults to 8 data bits, 1 stop bit, and no parity
233 default TTYS0_LCS=0x3
236 ### Select the coreboot loglevel
238 ## EMERG 1 system is unusable
239 ## ALERT 2 action must be taken immediately
240 ## CRIT 3 critical conditions
241 ## ERR 4 error conditions
242 ## WARNING 5 warning conditions
243 ## NOTICE 6 normal but significant condition
244 ## INFO 7 informational
245 ## DEBUG 8 debug-level messages
246 ## SPEW 9 Way too many details
248 ## Request this level of debugging output
249 default DEFAULT_CONSOLE_LOGLEVEL=8
250 ## At a maximum only compile in this level of debugging
251 default MAXIMUM_CONSOLE_LOGLEVEL=8
254 ## Select power on after power fail setting
255 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"