src/mainboard/tyan/s4880/Config.lb

   1 include /config/nofailovercalculation.lb
   2 default CONFIG_ROM_PAYLOAD = 1
   3
   4 arch i386 end
   5
   6
   7 ##
   8 ## Build the objects we have code for in this directory.
   9 ##
  10
  11 driver mainboard.o
  12 if HAVE_MP_TABLE object mptable.o end
  13 if HAVE_PIRQ_TABLE object irq_tables.o end
  14
  15         if CONFIG_USE_INIT
  16
  17                 makerule ./auto.o
  18                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  19                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  20                 end
  21
  22         else
  23
  24                 makerule ./auto.inc
  25                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  26                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
  27                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
  28                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
  29                         end
  30         end
  31
  32 ##
  33 ## Build our 16 bit and 32 bit coreboot entry code
  34 ##
  35 if USE_FALLBACK_IMAGE
  36         mainboardinit cpu/x86/16bit/entry16.inc
  37         ldscript /cpu/x86/16bit/entry16.lds
  38 end
  39
  40 mainboardinit cpu/x86/32bit/entry32.inc
  41
  42         if CONFIG_USE_INIT
  43                 ldscript /cpu/x86/32bit/entry32.lds
  44         end
  45
  46         if CONFIG_USE_INIT
  47                 ldscript /cpu/amd/car/cache_as_ram.lds
  48         end
  49
  50 ##
  51 ## Build our reset vector (This is where coreboot is entered)
  52 ##
  53 if USE_FALLBACK_IMAGE
  54         mainboardinit cpu/x86/16bit/reset16.inc
  55         ldscript /cpu/x86/16bit/reset16.lds
  56 else
  57         mainboardinit cpu/x86/32bit/reset32.inc
  58         ldscript /cpu/x86/32bit/reset32.lds
  59 end
  60
  61 ##
  62 ## Include an id string (For safe flashing)
  63 ##
  64 mainboardinit arch/i386/lib/id.inc
  65 ldscript /arch/i386/lib/id.lds
  66
  67         ##
  68         ## Setup Cache-As-Ram
  69         ##
  70         mainboardinit cpu/amd/car/cache_as_ram.inc
  71
  72 ###
  73 ### This is the early phase of coreboot startup
  74 ### Things are delicate and we test to see if we should
  75 ### failover to another image.
  76 ###
  77 if USE_FALLBACK_IMAGE
  78                 ldscript /arch/i386/lib/failover.lds
  79 end
  80
  81 ##
  82 ## Setup RAM
  83 ##
  84         if CONFIG_USE_INIT
  85                 initobject auto.o
  86         else
  87                 mainboardinit ./auto.inc
  88         end
  89
  90 ##
  91 ## Include the secondary Configuration files
  92 ##
  93 config chip.h
  94
  95 # sample config for tyan/s4880
  96 chip northbridge/amd/amdk8/root_complex
  97         device apic_cluster 0 on
  98                 chip cpu/amd/socket_940
  99                         device apic 0 on end
 100                 end
 101         end
 102
 103         device pci_domain 0 on
 104                 chip northbridge/amd/amdk8
 105                         device pci 18.0 on end # LDT0
 106                         device pci 18.0 on end # LDT1
 107                         device pci 18.0 on #  northbridge
 108                                 #  devices on link 2, link 2 == LDT 2
 109                                 chip southbridge/amd/amd8131
 110                                         # the on/off keyword is mandatory
 111                                         device pci 0.0 on
 112 #                                                chip drivers/lsi/53c1030
 113 #                                                        device pci 4.0 on end
 114 #                                                        device pci 4.1 on end
 115 #                                                        register "fw_address" = "0xfff8c000"
 116 #                                                end
 117                                                 chip drivers/pci/onboard
 118                                                         device pci 9.0 on end
 119                                                         device pci 9.1 on end
 120                                                 end
 121                                         end
 122                                         device pci 0.1 on end
 123                                         device pci 1.0 on end
 124                                         device pci 1.1 on end
 125                                 end
 126                                 chip southbridge/amd/amd8111
 127                                         # this "device pci 0.0" is the parent the next one
 128                                         # PCI bridge
 129                                         device pci 0.0 on
 130                                                 device pci 0.0 on end
 131                                                 device pci 0.1 on end
 132                                                 device pci 0.2 off end
 133                                                 device pci 1.0 off end
 134                                                 chip drivers/pci/onboard
 135                                                         device pci 6.0 on end
 136                                                         register "rom_address" = "0xfff80000"
 137                                                 end
 138                                         end
 139                                         device pci 1.0 on
 140                                                 chip superio/winbond/w83627hf
 141                                                         device pnp 2e.0 on #  Floppy
 142                                                                 io 0x60 = 0x3f0
 143                                                                 irq 0x70 = 6
 144                                                                 drq 0x74 = 2
 145                                                         end
 146                                                         device pnp 2e.1 off #  Parallel Port
 147                                                                 io 0x60 = 0x378
 148                                                                 irq 0x70 = 7
 149                                                         end
 150                                                         device pnp 2e.2 on #  Com1
 151                                                                 io 0x60 = 0x3f8
 152                                                                 irq 0x70 = 4
 153                                                         end
 154                                                         device pnp 2e.3 off #  Com2
 155                                                                 io 0x60 = 0x2f8
 156                                                                 irq 0x70 = 3
 157                                                         end
 158                                                         device pnp 2e.5 on #  Keyboard
 159                                                                 io 0x60 = 0x60
 160                                                                 io 0x62 = 0x64
 161                                                                 irq 0x70 = 1
 162                                                                 irq 0x72 = 12
 163                                                         end
 164                                                         device pnp 2e.6 off #  CIR
 165                                                                 io 0x60 = 0x100
 166                                                         end
 167                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 168                                                                 io 0x60 = 0x220
 169                                                                 io 0x62 = 0x300
 170                                                                 irq 0x70 = 9
 171                                                         end
 172                                                         device pnp 2e.8 off end #  GPIO2
 173                                                         device pnp 2e.9 off end #  GPIO3
 174                                                         device pnp 2e.a off end #  ACPI
 175                                                         device pnp 2e.b on #  HW Monitor
 176                                                                 io 0x60 = 0x290
 177                                                                 irq 0x70 = 5
 178                                                         end
 179                                                 end
 180                                         end
 181                                         device pci 1.1 on end
 182                                         device pci 1.2 on end
 183                                         device pci 1.3 on end
 184                                         device pci 1.5 off end
 185                                         device pci 1.6 off end
 186                                         register "ide0_enable" = "1"
 187                                         register "ide1_enable" = "1"
 188                                 end
 189                         end #  device pci 18.0
 190
 191                         device pci 18.1 on end
 192                         device pci 18.2 on end
 193                         device pci 18.3 on end
 194                 end
 195
 196         end #pci_domain
 197 end
 198