src/mainboard/tyan/s4880/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19
  20 ##
  21 ## Compute where this copy of linuxBIOS will start in the boot rom
  22 ##
  23 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  24
  25 ##
  26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  27 ## execution speed.
  28 ##
  29 ## XIP_ROM_SIZE must be a power of 2.
  30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  31 ##
  32 default XIP_ROM_SIZE=65536
  33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  34
  35 arch i386 end
  36
  37 ##
  38 ## Build the objects we have code for in this directory.
  39 ##
  40
  41 driver mainboard.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44 #object reset.o
  45
  46 ##
  47 ## Romcc output
  48 ##
  49 makerule ./failover.E
  50         depends "$(MAINBOARD)/failover.c ./romcc"
  51         action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  52 end
  53
  54 makerule ./failover.inc
  55         depends "$(MAINBOARD)/failover.c ./romcc"
  56         action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  57 end
  58
  59 makerule ./auto.E
  60         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  61         action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  62 end
  63 makerule ./auto.inc
  64         depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  65         action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  66 end
  67
  68 ##
  69 ## Setup RAM
  70 ##
  71 mainboardinit cpu/x86/fpu/enable_fpu.inc
  72 mainboardinit cpu/x86/mmx/enable_mmx.inc
  73 mainboardinit cpu/x86/sse/enable_sse.inc
  74 mainboardinit ./auto.inc
  75 mainboardinit cpu/x86/sse/disable_sse.inc
  76 mainboardinit cpu/x86/mmx/disable_mmx.inc
  77 mainboardinit arch/i386/lib/jmp_auto_out.inc
  78
  79 ##
  80 ## Build our 16 bit and 32 bit linuxBIOS entry code
  81 ##
  82 mainboardinit cpu/x86/16bit/entry16.inc
  83 mainboardinit cpu/x86/32bit/entry32.inc
  84 ldscript /cpu/x86/16bit/entry16.lds
  85 ldscript /cpu/x86/32bit/entry32.lds
  86
  87 ##
  88 ## Build our reset vector (This is where linuxBIOS is entered)
  89 ##
  90 if USE_FALLBACK_IMAGE
  91         mainboardinit cpu/x86/16bit/reset16.inc
  92         ldscript /cpu/x86/16bit/reset16.lds
  93 else
  94         mainboardinit cpu/x86/32bit/reset32.inc
  95         ldscript /cpu/x86/32bit/reset32.lds
  96 end
  97
  98 ### Should this be in the northbridge code?
  99 mainboardinit arch/i386/lib/cpu_reset.inc
 100
 101 ##
 102 ## Include an id string (For safe flashing)
 103 ##
 104 mainboardinit arch/i386/lib/id.inc
 105 ldscript /arch/i386/lib/id.lds
 106
 107 ###
 108 ### This is the early phase of linuxBIOS startup
 109 ### Things are delicate and we test to see if we should
 110 ### failover to another image.
 111 ###
 112 if USE_FALLBACK_IMAGE
 113         ldscript /arch/i386/lib/failover.lds
 114         mainboardinit ./failover.inc
 115 end
 116
 117 ###
 118 ### O.k. We aren't just an intermediary anymore!
 119 ###
 120
 121 mainboardinit arch/i386/lib/jmp_auto.inc
 122
 123 ##
 124 ## Include the secondary Configuration files
 125 ##
 126 if CONFIG_CHIP_NAME
 127         config chip.h
 128 end
 129
 130 # sample config for tyan/s4880
 131 chip northbridge/amd/amdk8/root_complex
 132         device apic_cluster 0 on
 133                 chip cpu/amd/socket_940
 134                         device apic 0 on end
 135                 end
 136         end
 137
 138         device pci_domain 0 on
 139                 chip northbridge/amd/amdk8
 140                         device pci 18.0 on end # LDT0
 141                         device pci 18.0 on end # LDT1
 142                         device pci 18.0 on #  northbridge
 143                                 #  devices on link 2, link 2 == LDT 2
 144                                 chip southbridge/amd/amd8131
 145                                         # the on/off keyword is mandatory
 146                                         device pci 0.0 on
 147                                                 chip drivers/lsi/53c1030
 148                                                         device pci 4.0 on end
 149                                                         device pci 4.1 on end
 150                                                         register "fw_address" = "0xfff8c000"
 151                                                 end
 152                                                 chip drivers/pci/onboard
 153                                                         device pci 9.0 on end
 154                                                         device pci 9.1 on end
 155                                                 end
 156                                         end
 157                                         device pci 0.1 on end
 158                                         device pci 1.0 on end
 159                                         device pci 1.1 on end
 160                                 end
 161                                 chip southbridge/amd/amd8111
 162                                         # this "device pci 0.0" is the parent the next one
 163                                         # PCI bridge
 164                                         device pci 0.0 on
 165                                                 device pci 0.0 on end
 166                                                 device pci 0.1 on end
 167                                                 device pci 0.2 off end
 168                                                 device pci 1.0 off end
 169                                                 chip drivers/pci/onboard
 170                                                         device pci 6.0 on end
 171                                                         register "rom_address" = "0xfff80000"
 172                                                 end
 173                                         end
 174                                         device pci 1.0 on
 175                                                 chip superio/winbond/w83627hf
 176                                                         device pnp 2e.0 on #  Floppy
 177                                                                 io 0x60 = 0x3f0
 178                                                                 irq 0x70 = 6
 179                                                                 drq 0x74 = 2
 180                                                         end
 181                                                         device pnp 2e.1 off #  Parallel Port
 182                                                                 io 0x60 = 0x378
 183                                                                 irq 0x70 = 7
 184                                                         end
 185                                                         device pnp 2e.2 on #  Com1
 186                                                                 io 0x60 = 0x3f8
 187                                                                 irq 0x70 = 4
 188                                                         end
 189                                                         device pnp 2e.3 off #  Com2
 190                                                                 io 0x60 = 0x2f8
 191                                                                 irq 0x70 = 3
 192                                                         end
 193                                                         device pnp 2e.5 on #  Keyboard
 194                                                                 io 0x60 = 0x60
 195                                                                 io 0x62 = 0x64
 196                                                                 irq 0x70 = 1
 197                                                                 irq 0x72 = 12
 198                                                         end
 199                                                         device pnp 2e.6 off #  CIR
 200                                                                 io 0x60 = 0x100
 201                                                         end
 202                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 203                                                                 io 0x60 = 0x220
 204                                                                 io 0x62 = 0x300
 205                                                                 irq 0x70 = 9
 206                                                         end
 207                                                         device pnp 2e.8 off end #  GPIO2
 208                                                         device pnp 2e.9 off end #  GPIO3
 209                                                         device pnp 2e.a off end #  ACPI
 210                                                         device pnp 2e.b on #  HW Monitor
 211                                                                 io 0x60 = 0x290
 212                                                                 irq 0x70 = 5
 213                                                         end
 214                                                 end
 215                                         end
 216                                         device pci 1.1 on end
 217                                         device pci 1.2 on end
 218                                         device pci 1.3 on end
 219                                         device pci 1.5 off end
 220                                         device pci 1.6 off end
 221                                         register "ide0_enable" = "1"
 222                                         register "ide1_enable" = "1"
 223                                 end
 224                         end #  device pci 18.0
 225
 226                         device pci 18.1 on end
 227                         device pci 18.2 on end
 228                         device pci 18.3 on end
 229                 end
 230
 231         end #pci_domain
 232 end
 233