3 uses USE_FALLBACK_IMAGE
4 uses LB_CKS_RANGE_START
10 uses HARD_RESET_DEVICE
11 uses HARD_RESET_FUNCTION
15 ### Set all of the defaults for an x86 architecture
20 ### Build the objects we have code for in this directory.
24 register "fixup_scsi" = "1"
25 #register "fixup_vga" = "1"
29 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
31 default LB_CKS_RANGE_START=49
32 default LB_CKS_RANGE_END=122
33 default LB_CKS_LOC=123
37 #driver adaptec_scsi.o
41 if HAVE_MP_TABLE object mptable.o end
42 if HAVE_PIRQ_TABLE object irq_tables.o end
44 default HARD_RESET_BUS=1
45 default HARD_RESET_DEVICE=4
46 default HARD_RESET_FUNCTION=0
52 ### Build our 16 bit and 32 bit linuxBIOS entry code
54 mainboardinit cpu/i386/entry16.inc
55 mainboardinit cpu/i386/entry32.inc
56 mainboardinit cpu/i386/bist32.inc
57 ldscript /cpu/i386/entry16.lds
58 ldscript /cpu/i386/entry32.lds
61 ### Build our reset vector (This is where linuxBIOS is entered)
64 mainboardinit cpu/i386/reset16.inc
65 ldscript /cpu/i386/reset16.lds
67 mainboardinit cpu/i386/reset32.inc
68 ldscript /cpu/i386/reset32.lds
71 #### Should this be in the northbridge code?
72 mainboardinit arch/i386/lib/cpu_reset.inc
75 ### Include an id string (For safe flashing)
77 mainboardinit arch/i386/lib/id.inc
78 ldscript /arch/i386/lib/id.lds
81 #### This is the early phase of linuxBIOS startup
82 #### Things are delicate and we test to see if we should
83 #### failover to another image.
85 #option MAX_REBOOT_CNT=2
87 ldscript /arch/i386/lib/failover.lds
93 mainboardinit cpu/k8/earlymtrr.inc
95 ### Only the bootstrap cpu makes it here.
96 ### Failover if we need to
100 mainboardinit ./failover.inc
106 ### Setup the serial port
108 mainboardinit pc80/serial.inc
109 mainboardinit arch/i386/lib/console.inc
110 mainboardinit cpu/i386/bist32_fail.inc
113 #### O.k. We aren't just an intermediary anymore!
119 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
120 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
121 #mainboardinit .failover.inc
123 makerule ./failover.E
124 depends "$(MAINBOARD)/failover.c"
125 action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
128 makerule ./failover.inc
129 depends "./romcc ./failover.E"
130 action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
133 depends "$(MAINBOARD)/auto.c option_table.h"
134 action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
137 depends "./romcc ./auto.E"
138 action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
139 # action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
141 mainboardinit cpu/k8/enable_mmx_sse.inc
142 mainboardinit ./auto.inc
143 mainboardinit cpu/k8/disable_mmx_sse.inc
146 ### Include the secondary Configuration files
148 northbridge amd/amdk8 "mc0"
155 southbridge amd/amd8131 "amd8131" link 2
161 southbridge amd/amd8111 "amd8111" link 2
173 superio winbond/w83627hf link 1
174 pnp 2e.0 off # Floppy
178 pnp 2e.1 off # Parallel Port
187 pnp 2e.5 on # Keyboard
192 pnp 2e.7 off # GAME_MIDI_GIPO1
196 pnp 2e.b off # HW Monitor
201 northbridge amd/amdk8 "mc1"
210 northbridge amd/amdk8 "mc2"
220 northbridge amd/amdk8 "mc3"
234 register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"