src/mainboard/tyan/s4880/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FALLBACK_IMAGE
   6         default ROM_SECTION_SIZE   = FALLBACK_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
   8 else
   9         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
  10         default ROM_SECTION_OFFSET = 0
  11 end
  12
  13 ##
  14 ## Compute the start location and size size of
  15 ## The linuxBIOS bootloader.
  16 ##
  17 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  19 default CONFIG_ROM_STREAM     = 1
  20
  21 ##
  22 ## Compute where this copy of linuxBIOS will start in the boot rom
  23 ##
  24 default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
  25
  26 ##
  27 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  28 ## execution speed.
  29 ##
  30 ## XIP_ROM_SIZE must be a power of 2.
  31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  32 ##
  33 default XIP_ROM_SIZE=65536
  34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
  35
  36 arch i386 end
  37
  38
  39 ##
  40 ## Build the objects we have code for in this directory.
  41 ##
  42
  43 driver mainboard.o
  44 if HAVE_MP_TABLE object mptable.o end
  45 if HAVE_PIRQ_TABLE object irq_tables.o end
  46 object reset.o
  47 if USE_DCACHE_RAM
  48
  49         if CONFIG_USE_INIT
  50
  51                 makerule ./auto.o
  52                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  53                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  54                 end
  55
  56         else
  57
  58                 makerule ./auto.inc
  59                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  60                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  61                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  62                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  63                         end
  64         end
  65 else
  66
  67         ##
  68         ## Romcc output
  69         ##
  70         makerule ./failover.E
  71                 depends "$(MAINBOARD)/failover.c ./romcc"
  72                 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  73         end
  74
  75         makerule ./failover.inc
  76                 depends "$(MAINBOARD)/failover.c ./romcc"
  77                 action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  78         end
  79
  80         makerule ./auto.E
  81                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  82                 action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  83         end
  84
  85         makerule ./auto.inc
  86                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  87                 action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  88         end
  89
  90         ##
  91         ## Setup RAM
  92         ##
  93         mainboardinit cpu/x86/fpu/enable_fpu.inc
  94         mainboardinit cpu/x86/mmx/enable_mmx.inc
  95         mainboardinit cpu/x86/sse/enable_sse.inc
  96         mainboardinit ./auto.inc
  97         mainboardinit cpu/x86/sse/disable_sse.inc
  98         mainboardinit cpu/x86/mmx/disable_mmx.inc
  99         mainboardinit arch/i386/lib/jmp_auto_out.inc
 100
 101 end
 102
 103 ##
 104 ## Build our 16 bit and 32 bit linuxBIOS entry code
 105 ##
 106 if USE_FALLBACK_IMAGE
 107         mainboardinit cpu/x86/16bit/entry16.inc
 108         ldscript /cpu/x86/16bit/entry16.lds
 109 end
 110
 111 mainboardinit cpu/x86/32bit/entry32.inc
 112
 113 if USE_DCACHE_RAM
 114         if CONFIG_USE_INIT
 115                 ldscript /cpu/x86/32bit/entry32.lds
 116         end
 117
 118         if CONFIG_USE_INIT
 119                 ldscript /cpu/amd/car/cache_as_ram.lds
 120         end
 121 end
 122
 123
 124 ##
 125 ## Build our reset vector (This is where linuxBIOS is entered)
 126 ##
 127 if USE_FALLBACK_IMAGE
 128         mainboardinit cpu/x86/16bit/reset16.inc
 129         ldscript /cpu/x86/16bit/reset16.lds
 130 else
 131         mainboardinit cpu/x86/32bit/reset32.inc
 132         ldscript /cpu/x86/32bit/reset32.lds
 133 end
 134
 135 if USE_DCACHE_RAM
 136 else
 137         ### Should this be in the northbridge code?
 138         mainboardinit arch/i386/lib/cpu_reset.inc
 139 end
 140
 141 ##
 142 ## Include an id string (For safe flashing)
 143 ##
 144 mainboardinit arch/i386/lib/id.inc
 145 ldscript /arch/i386/lib/id.lds
 146
 147
 148 if USE_DCACHE_RAM
 149         ##
 150         ## Setup Cache-As-Ram
 151         ##
 152         mainboardinit cpu/amd/car/cache_as_ram.inc
 153 end
 154
 155 ###
 156 ### This is the early phase of linuxBIOS startup
 157 ### Things are delicate and we test to see if we should
 158 ### failover to another image.
 159 ###
 160 if USE_FALLBACK_IMAGE
 161         if USE_DCACHE_RAM
 162                 ldscript /arch/i386/lib/failover.lds
 163         else
 164                 ldscript /arch/i386/lib/failover.lds
 165                 mainboardinit ./failover.inc
 166         end
 167 end
 168
 169 ##
 170 ## Setup RAM
 171 ##
 172 if USE_DCACHE_RAM
 173
 174         if CONFIG_USE_INIT
 175                 initobject auto.o
 176         else
 177                 mainboardinit ./auto.inc
 178         end
 179
 180 else
 181
 182         # ROMCC
 183         mainboardinit arch/i386/lib/jmp_auto.inc
 184
 185 end
 186
 187 ##
 188 ## Include the secondary Configuration files
 189 ##
 190 if CONFIG_CHIP_NAME
 191         config chip.h
 192 end
 193
 194 # sample config for tyan/s4880
 195 chip northbridge/amd/amdk8/root_complex
 196         device apic_cluster 0 on
 197                 chip cpu/amd/socket_940
 198                         device apic 0 on end
 199                 end
 200         end
 201
 202         device pci_domain 0 on
 203                 chip northbridge/amd/amdk8
 204                         device pci 18.0 on end # LDT0
 205                         device pci 18.0 on end # LDT1
 206                         device pci 18.0 on #  northbridge
 207                                 #  devices on link 2, link 2 == LDT 2
 208                                 chip southbridge/amd/amd8131
 209                                         # the on/off keyword is mandatory
 210                                         device pci 0.0 on
 211 #                                                chip drivers/lsi/53c1030
 212 #                                                        device pci 4.0 on end
 213 #                                                        device pci 4.1 on end
 214 #                                                        register "fw_address" = "0xfff8c000"
 215 #                                                end
 216                                                 chip drivers/pci/onboard
 217                                                         device pci 9.0 on end
 218                                                         device pci 9.1 on end
 219                                                 end
 220                                         end
 221                                         device pci 0.1 on end
 222                                         device pci 1.0 on end
 223                                         device pci 1.1 on end
 224                                 end
 225                                 chip southbridge/amd/amd8111
 226                                         # this "device pci 0.0" is the parent the next one
 227                                         # PCI bridge
 228                                         device pci 0.0 on
 229                                                 device pci 0.0 on end
 230                                                 device pci 0.1 on end
 231                                                 device pci 0.2 off end
 232                                                 device pci 1.0 off end
 233                                                 chip drivers/pci/onboard
 234                                                         device pci 6.0 on end
 235                                                         register "rom_address" = "0xfff80000"
 236                                                 end
 237                                         end
 238                                         device pci 1.0 on
 239                                                 chip superio/winbond/w83627hf
 240                                                         device pnp 2e.0 on #  Floppy
 241                                                                 io 0x60 = 0x3f0
 242                                                                 irq 0x70 = 6
 243                                                                 drq 0x74 = 2
 244                                                         end
 245                                                         device pnp 2e.1 off #  Parallel Port
 246                                                                 io 0x60 = 0x378
 247                                                                 irq 0x70 = 7
 248                                                         end
 249                                                         device pnp 2e.2 on #  Com1
 250                                                                 io 0x60 = 0x3f8
 251                                                                 irq 0x70 = 4
 252                                                         end
 253                                                         device pnp 2e.3 off #  Com2
 254                                                                 io 0x60 = 0x2f8
 255                                                                 irq 0x70 = 3
 256                                                         end
 257                                                         device pnp 2e.5 on #  Keyboard
 258                                                                 io 0x60 = 0x60
 259                                                                 io 0x62 = 0x64
 260                                                                 irq 0x70 = 1
 261                                                                 irq 0x72 = 12
 262                                                         end
 263                                                         device pnp 2e.6 off #  CIR
 264                                                                 io 0x60 = 0x100
 265                                                         end
 266                                                         device pnp 2e.7 off #  GAME_MIDI_GIPO1
 267                                                                 io 0x60 = 0x220
 268                                                                 io 0x62 = 0x300
 269                                                                 irq 0x70 = 9
 270                                                         end
 271                                                         device pnp 2e.8 off end #  GPIO2
 272                                                         device pnp 2e.9 off end #  GPIO3
 273                                                         device pnp 2e.a off end #  ACPI
 274                                                         device pnp 2e.b on #  HW Monitor
 275                                                                 io 0x60 = 0x290
 276                                                                 irq 0x70 = 5
 277                                                         end
 278                                                 end
 279                                         end
 280                                         device pci 1.1 on end
 281                                         device pci 1.2 on end
 282                                         device pci 1.3 on end
 283                                         device pci 1.5 off end
 284                                         device pci 1.6 off end
 285                                         register "ide0_enable" = "1"
 286                                         register "ide1_enable" = "1"
 287                                 end
 288                         end #  device pci 18.0
 289
 290                         device pci 18.1 on end
 291                         device pci 18.2 on end
 292                         device pci 18.3 on end
 293                 end
 294
 295         end #pci_domain
 296 end
 297