src/mainboard/tyan/s4880/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12 #
  13 #
  14 ###
  15 ### Set all of the defaults for an x86 architecture
  16 ###
  17 #
  18 #
  19 ###
  20 ### Build the objects we have code for in this directory.
  21 ###
  22 ##object mainboard.o
  23 config chip.h
  24 register "fixup_scsi" = "1"
  25 #register "fixup_vga" = "1"
  26
  27
  28 ##
  29 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  30 ##
  31 default LB_CKS_RANGE_START=49
  32 default LB_CKS_RANGE_END=122
  33 default LB_CKS_LOC=123
  34
  35 driver mainboard.o
  36 driver lsi_scsi.o
  37 #driver adaptec_scsi.o
  38 driver si_sata.o
  39 #driver intel_nic.o
  40 #object reset.o
  41 if HAVE_MP_TABLE object mptable.o end
  42 if HAVE_PIRQ_TABLE object irq_tables.o end
  43 #
  44 default HARD_RESET_BUS=1
  45 default HARD_RESET_DEVICE=4
  46 default HARD_RESET_FUNCTION=0
  47 #
  48 arch i386 end
  49 #cpu k8 end
  50 #
  51 ###
  52 ### Build our 16 bit and 32 bit linuxBIOS entry code
  53 ###
  54 mainboardinit cpu/i386/entry16.inc
  55 mainboardinit cpu/i386/entry32.inc
  56 mainboardinit cpu/i386/bist32.inc
  57 ldscript /cpu/i386/entry16.lds
  58 ldscript /cpu/i386/entry32.lds
  59 #
  60 ###
  61 ### Build our reset vector (This is where linuxBIOS is entered)
  62 ###
  63 if USE_FALLBACK_IMAGE
  64         mainboardinit cpu/i386/reset16.inc
  65         ldscript /cpu/i386/reset16.lds
  66 else
  67         mainboardinit cpu/i386/reset32.inc
  68         ldscript /cpu/i386/reset32.lds
  69 end
  70 #
  71 #### Should this be in the northbridge code?
  72 mainboardinit arch/i386/lib/cpu_reset.inc
  73 #
  74 ###
  75 ### Include an id string (For safe flashing)
  76 ###
  77 mainboardinit arch/i386/lib/id.inc
  78 ldscript /arch/i386/lib/id.lds
  79 #
  80 ####
  81 #### This is the early phase of linuxBIOS startup
  82 #### Things are delicate and we test to see if we should
  83 #### failover to another image.
  84 ####
  85 #option MAX_REBOOT_CNT=2
  86 if USE_FALLBACK_IMAGE
  87   ldscript /arch/i386/lib/failover.lds
  88 end
  89 #
  90 ###
  91 ### Setup our mtrrs
  92 ###
  93 mainboardinit cpu/k8/earlymtrr.inc
  94 ###
  95 ### Only the bootstrap cpu makes it here.
  96 ### Failover if we need to
  97 ###
  98 #
  99 if USE_FALLBACK_IMAGE
 100   mainboardinit ./failover.inc
 101 end
 102
 103 #
 104 #
 105 ###
 106 ### Setup the serial port
 107 ###
 108 mainboardinit pc80/serial.inc
 109 mainboardinit arch/i386/lib/console.inc
 110 mainboardinit cpu/i386/bist32_fail.inc
 111 #
 112 ####
 113 #### O.k. We aren't just an intermediary anymore!
 114 ####
 115 #
 116 ###
 117 ### Romcc output
 118 ###
 119 #makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
 120 #makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
 121 #mainboardinit .failover.inc
 122
 123 makerule ./failover.E
 124         depends "$(MAINBOARD)/failover.c"
 125         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 126 end
 127
 128 makerule ./failover.inc
 129         depends "./romcc ./failover.E"
 130         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 131
 132 makerule ./auto.E
 133         depends "$(MAINBOARD)/auto.c option_table.h"
 134         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 135 end
 136 makerule ./auto.inc
 137         depends "./romcc ./auto.E"
 138         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 139 #       action  "./romcc -mcpu=k8  -O ./auto.E > auto.inc"
 140 end
 141 mainboardinit cpu/k8/enable_mmx_sse.inc
 142 mainboardinit ./auto.inc
 143 mainboardinit cpu/k8/disable_mmx_sse.inc
 144 #
 145 ###
 146 ### Include the secondary Configuration files
 147 ###
 148 northbridge amd/amdk8 "mc0"
 149         pci 0:18.0
 150         pci 0:18.0
 151         pci 0:18.0
 152         pci 0:18.1
 153         pci 0:18.2
 154         pci 0:18.3
 155         southbridge amd/amd8131 "amd8131" link 2
 156                 pci 0:0.0
 157                 pci 0:0.1
 158                 pci 0:1.0
 159                 pci 0:1.1
 160         end
 161         southbridge amd/amd8111 "amd8111" link 2
 162                 pci 0:0.0
 163                 pci 0:1.0 on
 164                 pci 0:1.1 on
 165                 pci 0:1.2 on
 166                 pci 0:1.3 on
 167                 pci 0:1.5 off
 168                 pci 0:1.6 off
 169                 pci 1:0.0 on
 170                 pci 1:0.1 on
 171                 pci 1:0.2 on
 172                 pci 1:1.0 off
 173                 superio winbond/w83627hf link 1
 174                         pnp 2e.0 off #  Floppy
 175                                  io 0x60 = 0x3f0
 176                                 irq 0x70 = 6
 177                                 drq 0x74 = 2
 178                         pnp 2e.1 off #  Parallel Port
 179                                  io 0x60 = 0x378
 180                                 irq 0x70 = 7
 181                         pnp 2e.2 on #  Com1
 182                                  io 0x60 = 0x3f8
 183                                 irq 0x70 = 4
 184                         pnp 2e.3 off #  Com2
 185                                  io 0x60 = 0x2f8
 186                                 irq 0x70 = 3
 187                         pnp 2e.5 on #  Keyboard
 188                                  io 0x60 = 0x60
 189                                  io 0x62 = 0x64
 190                                 irq 0x70 = 1
 191                         pnp 2e.6 off #  CIR
 192                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 193                         pnp 2e.8 off #  GPIO2
 194                         pnp 2e.9 off #  GPIO3
 195                         pnp 2e.a off #  ACPI
 196                         pnp 2e.b off #  HW Monitor
 197                 end
 198         end
 199 end
 200
 201 northbridge amd/amdk8 "mc1"
 202         pci 0:19.0
 203         pci 0:19.0
 204         pci 0:19.0
 205         pci 0:19.1
 206         pci 0:19.2
 207         pci 0:19.3
 208 end
 209
 210 northbridge amd/amdk8 "mc2"
 211         pci 0:1a.0
 212         pci 0:1a.0
 213         pci 0:1a.0
 214         pci 0:1a.1
 215         pci 0:1a.2
 216         pci 0:1a.3
 217 end
 218
 219
 220 northbridge amd/amdk8 "mc3"
 221         pci 0:1b.0
 222         pci 0:1b.0
 223         pci 0:1b.0
 224         pci 0:1b.1
 225         pci 0:1b.2
 226         pci 0:1b.3
 227 end
 228
 229
 230 dir /pc80
 231 #dir /bioscall
 232
 233 cpu k8 "cpu0"
 234   register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 235 end
 236
 237 cpu k8 "cpu1"
 238 end
 239
 240 cpu k8 "cpu2"
 241 end
 242
 243 cpu k8 "cpu3"
 244 end