2 ## Compute the location and size of where this firmware image
3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The linuxBIOS bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
21 ## Compute where this copy of linuxBIOS will start in the boot rom
23 default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
26 ## Compute a range of ROM that can cached to speed up linuxBIOS,
29 ## XIP_ROM_SIZE must be a power of 2.
30 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
32 default XIP_ROM_SIZE=65536
33 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
38 ## Build the objects we have code for in this directory.
42 if HAVE_MP_TABLE object mptable.o end
43 if HAVE_PIRQ_TABLE object irq_tables.o end
50 depends "$(MAINBOARD)/failover.c ./romcc"
51 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
54 makerule ./failover.inc
55 depends "$(MAINBOARD)/failover.c ./romcc"
56 action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
60 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
61 action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
64 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
65 action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
69 ## Build our 16 bit and 32 bit linuxBIOS entry code
71 mainboardinit cpu/x86/16bit/entry16.inc
72 mainboardinit cpu/x86/32bit/entry32.inc
73 ldscript /cpu/x86/16bit/entry16.lds
74 ldscript /cpu/x86/32bit/entry32.lds
77 ## Build our reset vector (This is where linuxBIOS is entered)
80 mainboardinit cpu/x86/16bit/reset16.inc
81 ldscript /cpu/x86/16bit/reset16.lds
83 mainboardinit cpu/x86/32bit/reset32.inc
84 ldscript /cpu/x86/32bit/reset32.lds
87 ### Should this be in the northbridge code?
88 mainboardinit arch/i386/lib/cpu_reset.inc
91 ## Include an id string (For safe flashing)
93 mainboardinit arch/i386/lib/id.inc
94 ldscript /arch/i386/lib/id.lds
97 ### This is the early phase of linuxBIOS startup
98 ### Things are delicate and we test to see if we should
99 ### failover to another image.
101 if USE_FALLBACK_IMAGE
102 ldscript /arch/i386/lib/failover.lds
103 mainboardinit ./failover.inc
107 ### O.k. We aren't just an intermediary anymore!
113 mainboardinit cpu/x86/fpu/enable_fpu.inc
114 mainboardinit cpu/x86/mmx/enable_mmx.inc
115 mainboardinit cpu/x86/sse/enable_sse.inc
116 mainboardinit ./auto.inc
117 mainboardinit cpu/x86/sse/disable_sse.inc
118 mainboardinit cpu/x86/mmx/disable_mmx.inc
121 ## Include the secondary Configuration files
126 # sample config for tyan/s4880
127 chip northbridge/amd/amdk8
128 device pci_domain 0 on
129 device pci 18.0 on end # LDT0
130 device pci 18.0 on end # LDT1
131 device pci 18.0 on # northbridge
132 # devices on link 2, link 2 == LDT 2
133 chip southbridge/amd/amd8131
134 # the on/off keyword is mandatory
135 device pci 0.0 on end
136 device pci 0.1 on end
137 device pci 1.0 on end
138 device pci 1.1 on end
140 chip southbridge/amd/amd8111
141 # this "device pci 0.0" is the parent the next one
144 device pci 0.0 on end
145 device pci 0.1 on end
146 device pci 0.2 off end
147 device pci 1.0 off end
150 chip superio/winbond/w83627hf
151 device pnp 2e.0 on # Floppy
156 device pnp 2e.1 off # Parallel Port
160 device pnp 2e.2 on # Com1
164 device pnp 2e.3 off # Com2
168 device pnp 2e.5 on # Keyboard
174 device pnp 2e.6 off # CIR
177 device pnp 2e.7 off # GAME_MIDI_GIPO1
182 device pnp 2e.8 off end # GPIO2
183 device pnp 2e.9 off end # GPIO3
184 device pnp 2e.a off end # ACPI
185 device pnp 2e.b on # HW Monitor
191 device pci 1.1 on end
192 device pci 1.2 on end
193 device pci 1.3 on end
194 device pci 1.5 off end
195 device pci 1.6 off end
197 end # device pci 18.0
199 device pci 18.1 on end
200 device pci 18.2 on end
201 device pci 18.3 on end
203 chip northbridge/amd/amdk8
204 device pci 19.0 on end
205 device pci 19.0 on end
206 device pci 19.0 on end
207 device pci 19.1 on end
208 device pci 19.2 on end
209 device pci 19.3 on end
212 chip northbridge/amd/amdk8
213 device pci 1a.0 on end
214 device pci 1a.0 on end
215 device pci 1a.0 on end
216 device pci 1a.1 on end
217 device pci 1a.2 on end
218 device pci 1a.3 on end
221 chip northbridge/amd/amdk8
222 device pci 1b.0 on end
223 device pci 1b.0 on end
224 device pci 1b.0 on end
225 device pci 1b.1 on end
226 device pci 1b.2 on end
227 device pci 1b.3 on end
230 device apic_cluster 0 on
231 chip cpu/amd/socket_940
234 chip cpu/amd/socket_940
237 chip cpu/amd/socket_940
240 chip cpu/amd/socket_940