src/mainboard/tyan/s4880/Config.lb

   1 uses HAVE_MP_TABLE
   2 uses HAVE_PIRQ_TABLE
   3 uses USE_FALLBACK_IMAGE
   4 uses LB_CKS_RANGE_START
   5 uses LB_CKS_RANGE_END
   6 uses LB_CKS_LOC
   7 uses MAINBOARD
   8 uses ARCH
   9 uses HARD_RESET_BUS
  10 uses HARD_RESET_DEVICE
  11 uses HARD_RESET_FUNCTION
  12 #
  13 #
  14 ###
  15 ### Set all of the defaults for an x86 architecture
  16 ###
  17 #
  18 #
  19 ###
  20 ### Build the objects we have code for in this directory.
  21 ###
  22 ##object mainboard.o
  23 config chip.h
  24 register "fixup_scsi" = "1"
  25 #register "fixup_vga" = "1"
  26
  27
  28 ##
  29 ## Move the default LinuxBIOS cmos range off of AMD RTC registers
  30 ##
  31 default LB_CKS_RANGE_START=49
  32 default LB_CKS_RANGE_END=122
  33 default LB_CKS_LOC=123
  34
  35 driver mainboard.o
  36 #dir /drivers/lsi/53c1030
  37 #dir /drivers/adaptec/7902
  38 #dir /drivers/si/3114
  39 #dir /drivers/intel/82551
  40 #dir /drivers/ati/ragexl
  41 #object reset.o
  42 if HAVE_MP_TABLE object mptable.o end
  43 if HAVE_PIRQ_TABLE object irq_tables.o end
  44 #
  45 default HARD_RESET_BUS=1
  46 default HARD_RESET_DEVICE=4
  47 default HARD_RESET_FUNCTION=0
  48 #
  49 arch i386 end
  50 #cpu k8 end
  51 #
  52 ###
  53 ### Build our 16 bit and 32 bit linuxBIOS entry code
  54 ###
  55 mainboardinit cpu/i386/entry16.inc
  56 mainboardinit cpu/i386/entry32.inc
  57 mainboardinit cpu/i386/bist32.inc
  58 ldscript /cpu/i386/entry16.lds
  59 ldscript /cpu/i386/entry32.lds
  60 #
  61 ###
  62 ### Build our reset vector (This is where linuxBIOS is entered)
  63 ###
  64 if USE_FALLBACK_IMAGE
  65         mainboardinit cpu/i386/reset16.inc
  66         ldscript /cpu/i386/reset16.lds
  67 else
  68         mainboardinit cpu/i386/reset32.inc
  69         ldscript /cpu/i386/reset32.lds
  70 end
  71 #
  72 #### Should this be in the northbridge code?
  73 mainboardinit arch/i386/lib/cpu_reset.inc
  74 #
  75 ###
  76 ### Include an id string (For safe flashing)
  77 ###
  78 mainboardinit arch/i386/lib/id.inc
  79 ldscript /arch/i386/lib/id.lds
  80 #
  81 ####
  82 #### This is the early phase of linuxBIOS startup
  83 #### Things are delicate and we test to see if we should
  84 #### failover to another image.
  85 ####
  86 #option MAX_REBOOT_CNT=2
  87 if USE_FALLBACK_IMAGE
  88   ldscript /arch/i386/lib/failover.lds
  89 end
  90 #
  91 ###
  92 ### Setup our mtrrs
  93 ###
  94 mainboardinit cpu/k8/earlymtrr.inc
  95 ###
  96 ### Only the bootstrap cpu makes it here.
  97 ### Failover if we need to
  98 ###
  99 #
 100 if USE_FALLBACK_IMAGE
 101   mainboardinit ./failover.inc
 102 end
 103
 104 #
 105 #
 106 ###
 107 ### Setup the serial port
 108 ###
 109 mainboardinit pc80/serial.inc
 110 mainboardinit arch/i386/lib/console.inc
 111 mainboardinit cpu/i386/bist32_fail.inc
 112 #
 113 ####
 114 #### O.k. We aren't just an intermediary anymore!
 115 ####
 116 #
 117 ###
 118 ### Romcc output
 119 ###
 120
 121 makerule ./failover.E
 122         depends "$(MAINBOARD)/failover.c"
 123         action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 124 end
 125
 126 makerule ./failover.inc
 127         depends "./romcc ./failover.E"
 128         action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
 129
 130 makerule ./auto.E
 131         depends "$(MAINBOARD)/auto.c option_table.h"
 132         action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 133 end
 134 makerule ./auto.inc
 135         depends "./romcc ./auto.E"
 136         action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
 137 end
 138 mainboardinit cpu/k8/enable_mmx_sse.inc
 139 mainboardinit ./auto.inc
 140 mainboardinit cpu/k8/disable_mmx_sse.inc
 141 #
 142 ###
 143 ### Include the secondary Configuration files
 144 ###
 145 northbridge amd/amdk8 "mc0"
 146         pci 0:18.0
 147         pci 0:18.0
 148         pci 0:18.0
 149         pci 0:18.1
 150         pci 0:18.2
 151         pci 0:18.3
 152         southbridge amd/amd8131 "amd8131" link 2
 153                 pci 0:0.0
 154                 pci 0:0.1
 155                 pci 0:1.0
 156                 pci 0:1.1
 157         end
 158         southbridge amd/amd8111 "amd8111" link 2
 159                 pci 0:0.0
 160                 pci 0:1.0 on
 161                 pci 0:1.1 on
 162                 pci 0:1.2 on
 163                 pci 0:1.3 on
 164                 pci 0:1.5 off
 165                 pci 0:1.6 off
 166                 pci 1:0.0 on
 167                 pci 1:0.1 on
 168                 pci 1:0.2 on
 169                 pci 1:1.0 off
 170                 superio winbond/w83627hf link 1
 171                         pnp 2e.0 off #  Floppy
 172                                  io 0x60 = 0x3f0
 173                                 irq 0x70 = 6
 174                                 drq 0x74 = 2
 175                         pnp 2e.1 off #  Parallel Port
 176                                  io 0x60 = 0x378
 177                                 irq 0x70 = 7
 178                         pnp 2e.2 on #  Com1
 179                                  io 0x60 = 0x3f8
 180                                 irq 0x70 = 4
 181                         pnp 2e.3 off #  Com2
 182                                  io 0x60 = 0x2f8
 183                                 irq 0x70 = 3
 184                         pnp 2e.5 on #  Keyboard
 185                                  io 0x60 = 0x60
 186                                  io 0x62 = 0x64
 187                                 irq 0x70 = 1
 188                                 irq 0x72 = 12
 189                         pnp 2e.6 off #  CIR
 190                         pnp 2e.7 off #  GAME_MIDI_GIPO1
 191                         pnp 2e.8 off #  GPIO2
 192                         pnp 2e.9 off #  GPIO3
 193                         pnp 2e.a off #  ACPI
 194                         pnp 2e.b on  #  HW Monitor
 195                                  io 0x60 = 0x290
 196                 end
 197         end
 198 end
 199
 200 northbridge amd/amdk8 "mc1"
 201         pci 0:19.0
 202         pci 0:19.0
 203         pci 0:19.0
 204         pci 0:19.1
 205         pci 0:19.2
 206         pci 0:19.3
 207 end
 208
 209 northbridge amd/amdk8 "mc2"
 210         pci 0:1a.0
 211         pci 0:1a.0
 212         pci 0:1a.0
 213         pci 0:1a.1
 214         pci 0:1a.2
 215         pci 0:1a.3
 216 end
 217
 218
 219 northbridge amd/amdk8 "mc3"
 220         pci 0:1b.0
 221         pci 0:1b.0
 222         pci 0:1b.0
 223         pci 0:1b.1
 224         pci 0:1b.2
 225         pci 0:1b.3
 226 end
 227
 228
 229 dir /pc80
 230 #dir /bioscall
 231
 232 cpu k8 "cpu0"
 233   register "down" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
 234 end
 235
 236 cpu k8 "cpu1"
 237 end
 238
 239 cpu k8 "cpu2"
 240 end
 241
 242 cpu k8 "cpu3"
 243 end