2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
26 uses USE_FALLBACK_IMAGE
27 uses USE_FAILOVER_IMAGE
28 uses HAVE_FALLBACK_BOOT
29 uses HAVE_FAILOVER_BOOT
32 uses HAVE_OPTION_TABLE
34 uses CONFIG_MAX_PHYSICAL_CPUS
35 uses CONFIG_LOGICAL_CPUS
44 uses ROM_SECTION_OFFSET
45 uses CONFIG_ROM_PAYLOAD
46 uses CONFIG_ROM_PAYLOAD_START
47 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
48 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
56 uses LB_CKS_RANGE_START
59 uses MAINBOARD_PART_NUMBER
62 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
63 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
64 uses COREBOOT_EXTRA_VERSION
69 uses DEFAULT_CONSOLE_LOGLEVEL
70 uses MAXIMUM_CONSOLE_LOGLEVEL
71 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
72 uses CONFIG_CONSOLE_SERIAL8250
81 uses CONFIG_CONSOLE_VGA
82 uses CONFIG_USBDEBUG_DIRECT
83 uses CONFIG_PCI_ROM_RUN
84 uses HW_MEM_HOLE_SIZEK
85 uses HW_MEM_HOLE_SIZE_AUTO_INC
87 uses HT_CHAIN_UNITID_BASE
88 uses HT_CHAIN_END_UNITID_BASE
89 uses SB_HT_CHAIN_ON_BUS0
90 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
95 uses DCACHE_RAM_GLOBAL_VAR_SIZE
100 uses ENABLE_APIC_EXT_ID
102 uses LIFT_BSP_APIC_ID
104 uses CONFIG_PCI_64BIT_PREF_MEM
106 uses CONFIG_LB_MEM_TOPK
108 uses PCI_BUS_SEGN_BITS
110 uses CONFIG_AP_CODE_IN_CAR
114 uses WAIT_BEFORE_CPUS_INIT
118 uses CONFIG_USE_PRINTK_IN_CAR
120 uses AMD_UCODE_PATCH_FILE
127 ## ROM_SIZE is the size of boot ROM that this board will use.
129 default ROM_SIZE=524288
130 #default ROM_SIZE=0x100000
133 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
135 #default FALLBACK_SIZE=131072
136 #default FALLBACK_SIZE=0x40000
138 #FALLBACK: ROM_SIZE-4K
139 default FALLBACK_SIZE=ROM_SIZE-0x01000
141 default FAILOVER_SIZE=0x01000
144 default CONFIG_LB_MEM_TOPK=16384
147 ## Build code for the fallback boot
149 default HAVE_FALLBACK_BOOT=1
150 default HAVE_FAILOVER_BOOT=1
153 ## Build code to reset the motherboard from coreboot
155 default HAVE_HARD_RESET=1
158 ## Build code to export a programmable irq routing table
160 default HAVE_PIRQ_TABLE=1
161 default IRQ_SLOT_COUNT=11
164 ## Build code to export an x86 MP table
165 ## Useful for specifying IRQ routing values
167 default HAVE_MP_TABLE=1
169 ## ACPI tables will be included
170 default HAVE_ACPI_TABLES=0
172 default ACPI_SSDTX_NUM=31
175 ## Build code to export a CMOS option table
177 default HAVE_OPTION_TABLE=1
180 ## Move the default coreboot cmos range off of AMD RTC registers
182 default LB_CKS_RANGE_START=49
183 default LB_CKS_RANGE_END=122
184 default LB_CKS_LOC=123
187 ## Build code for SMP support
188 ## Only worry about 2 micro processors
191 default CONFIG_MAX_PHYSICAL_CPUS=2
192 default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
193 default CONFIG_LOGICAL_CPUS=1
195 #default SERIAL_CPU_INIT=0
197 default ENABLE_APIC_EXT_ID=1
198 default APIC_ID_OFFSET=0x00
199 default LIFT_BSP_APIC_ID=1
202 default CONFIG_CHIP_NAME=1
204 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
206 #default HW_MEM_HOLE_SIZEK=0x200000
208 default HW_MEM_HOLE_SIZEK=0x100000
210 #default HW_MEM_HOLE_SIZEK=0x80000
212 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
213 #default HW_MEM_HOLE_SIZE_AUTO_INC=1
216 default CONFIG_CONSOLE_VGA=1
217 default CONFIG_PCI_ROM_RUN=1
219 #default CONFIG_USBDEBUG_DIRECT=1
221 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
222 default HT_CHAIN_UNITID_BASE=1
224 #real SB Unit ID, default is 0x20, mean dont touch it at last
225 #default HT_CHAIN_END_UNITID_BASE=0x6
227 #make the SB HT chain on bus 0, default is not (0)
228 default SB_HT_CHAIN_ON_BUS0=2
230 #only offset for SB chain?, default is yes(1)
231 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
233 #allow capable device use that above 4G
234 #default CONFIG_PCI_64BIT_PREF_MEM=1
237 ## enable CACHE_AS_RAM specifics
239 default USE_DCACHE_RAM=1
240 default DCACHE_RAM_BASE=0xc4000
241 default DCACHE_RAM_SIZE=0x0c000
242 default DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
243 default CONFIG_USE_INIT=0
245 default MEM_TRAIN_SEQ=2
246 default WAIT_BEFORE_CPUS_INIT=0
247 default CONFIG_AMDMCT = 1
250 ## Build code to setup a generic IOAPIC
252 default CONFIG_IOAPIC=1
255 ## Clean up the motherboard id strings
257 default MAINBOARD_PART_NUMBER="S2912 (Fam10)"
258 default MAINBOARD_VENDOR="Tyan"
259 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
260 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
263 ## Set microcode patch file name
265 ## Barcelona rev Ax: "mc_patch_01000020.h"
266 ## Barcelona rev B0, B1, BA: "mc_patch_01000084.h"
267 ## Barcelona rev B2, B3: "mc_patch_01000083.h"
269 default AMD_UCODE_PATCH_FILE="mc_patch_01000083.h"
272 ### coreboot layout values
275 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
276 default ROM_IMAGE_SIZE = 65536
279 ## Use a small 8K stack
281 default STACK_SIZE=0x2000
284 ## Use a small 32K heap
286 default HEAP_SIZE=0xc0000
289 ## Only use the option table in a normal image
291 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
294 ## Coreboot C code runs at this location in RAM
296 default _RAMBASE=0x00200000
299 ## Load the payload from the ROM
301 default CONFIG_ROM_PAYLOAD = 1
303 #default CONFIG_COMPRESSED_PAYLOAD = 1
306 ### Defaults of options that you may want to override in the target config file
310 ## The default compiler
312 default CC="$(CROSS_COMPILE)gcc -m32"
316 ## Disable the gdb stub by default
318 default CONFIG_GDB_STUB=0
321 ## The Serial Console
323 default CONFIG_USE_PRINTK_IN_CAR=1
325 # To Enable the Serial Console
326 default CONFIG_CONSOLE_SERIAL8250=1
328 ## Select the serial console baud rate
329 default TTYS0_BAUD=115200
330 #default TTYS0_BAUD=57600
331 #default TTYS0_BAUD=38400
332 #default TTYS0_BAUD=19200
333 #default TTYS0_BAUD=9600
334 #default TTYS0_BAUD=4800
335 #default TTYS0_BAUD=2400
336 #default TTYS0_BAUD=1200
338 # Select the serial console base port
339 default TTYS0_BASE=0x3f8
341 # Select the serial protocol
342 # This defaults to 8 data bits, 1 stop bit, and no parity
343 default TTYS0_LCS=0x3
346 ### Select the coreboot loglevel
348 ## EMERG 1 system is unusable
349 ## ALERT 2 action must be taken immediately
350 ## CRIT 3 critical conditions
351 ## ERR 4 error conditions
352 ## WARNING 5 warning conditions
353 ## NOTICE 6 normal but significant condition
354 ## INFO 7 informational
355 ## DEBUG 8 debug-level messages
356 ## SPEW 9 Way too many details
358 ## Request this level of debugging output
359 default DEFAULT_CONSOLE_LOGLEVEL=8
360 ## At a maximum only compile in this level of debugging
361 default MAXIMUM_CONSOLE_LOGLEVEL=8
364 ## Select power on after power fail setting
365 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"