2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 uses CONFIG_HAVE_MP_TABLE
23 uses CONFIG_HAVE_PIRQ_TABLE
24 uses CONFIG_HAVE_ACPI_TABLES
25 uses CONFIG_HAVE_ACPI_RESUME
26 uses CONFIG_ACPI_SSDTX_NUM
27 uses CONFIG_USE_FALLBACK_IMAGE
28 uses CONFIG_USE_FAILOVER_IMAGE
29 uses CONFIG_HAVE_FALLBACK_BOOT
30 uses CONFIG_HAVE_FAILOVER_BOOT
31 uses CONFIG_HAVE_HARD_RESET
32 uses CONFIG_IRQ_SLOT_COUNT
33 uses CONFIG_HAVE_OPTION_TABLE
35 uses CONFIG_MAX_PHYSICAL_CPUS
36 uses CONFIG_LOGICAL_CPUS
39 uses CONFIG_FALLBACK_SIZE
40 uses CONFIG_FAILOVER_SIZE
42 uses CONFIG_ROM_SECTION_SIZE
43 uses CONFIG_ROM_IMAGE_SIZE
44 uses CONFIG_ROM_SECTION_SIZE
45 uses CONFIG_ROM_SECTION_OFFSET
46 uses CONFIG_ROM_PAYLOAD
47 uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
48 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
50 uses CONFIG_XIP_ROM_SIZE
51 uses CONFIG_XIP_ROM_BASE
52 uses CONFIG_STACK_SIZE
54 uses CONFIG_USE_OPTION_TABLE
55 uses CONFIG_LB_CKS_RANGE_START
56 uses CONFIG_LB_CKS_RANGE_END
57 uses CONFIG_LB_CKS_LOC
58 uses CONFIG_MAINBOARD_PART_NUMBER
59 uses CONFIG_MAINBOARD_VENDOR
61 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
62 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
63 uses COREBOOT_EXTRA_VERSION
65 uses CONFIG_TTYS0_BAUD
66 uses CONFIG_TTYS0_BASE
68 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
69 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
70 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
71 uses CONFIG_CONSOLE_SERIAL8250
72 uses CONFIG_HAVE_INIT_TIMER
75 uses CONFIG_CROSS_COMPILE
79 uses CONFIG_CONSOLE_VGA
80 uses CONFIG_USBDEBUG_DIRECT
81 uses CONFIG_PCI_ROM_RUN
82 uses CONFIG_HW_MEM_HOLE_SIZEK
83 uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
85 uses CONFIG_HT_CHAIN_UNITID_BASE
86 uses CONFIG_HT_CHAIN_END_UNITID_BASE
87 uses CONFIG_SB_HT_CHAIN_ON_BUS0
88 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
90 uses CONFIG_USE_DCACHE_RAM
91 uses CONFIG_DCACHE_RAM_BASE
92 uses CONFIG_DCACHE_RAM_SIZE
93 uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
96 uses CONFIG_SERIAL_CPU_INIT
98 uses CONFIG_ENABLE_APIC_EXT_ID
99 uses CONFIG_APIC_ID_OFFSET
100 uses CONFIG_LIFT_BSP_APIC_ID
102 uses CONFIG_PCI_64BIT_PREF_MEM
104 uses CONFIG_LB_MEM_TOPK
106 uses CONFIG_PCI_BUS_SEGN_BITS
108 uses CONFIG_AP_CODE_IN_CAR
110 uses CONFIG_MEM_TRAIN_SEQ
112 uses CONFIG_WAIT_BEFORE_CPUS_INIT
116 uses CONFIG_USE_PRINTK_IN_CAR
117 uses CONFIG_CAR_FAM10
118 uses CONFIG_AMD_UCODE_PATCH_FILE
125 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
127 default CONFIG_ROM_SIZE=1024*1024
128 #default CONFIG_ROM_SIZE=0x100000
131 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
134 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
135 default CONFIG_FAILOVER_SIZE=0x01000
138 default CONFIG_LB_MEM_TOPK=16384
141 ## Build code for the fallback boot
143 default CONFIG_HAVE_FALLBACK_BOOT=1
144 default CONFIG_HAVE_FAILOVER_BOOT=1
147 ## Build code to reset the motherboard from coreboot
149 default CONFIG_HAVE_HARD_RESET=1
152 ## Build code to export a programmable irq routing table
154 default CONFIG_HAVE_PIRQ_TABLE=1
155 default CONFIG_IRQ_SLOT_COUNT=11
158 ## Build code to export an x86 MP table
159 ## Useful for specifying IRQ routing values
161 default CONFIG_HAVE_MP_TABLE=1
163 ## ACPI tables will be included
164 default CONFIG_HAVE_ACPI_TABLES=0
166 default CONFIG_ACPI_SSDTX_NUM=31
169 ## Build code to export a CMOS option table
171 default CONFIG_HAVE_OPTION_TABLE=1
174 ## Move the default coreboot cmos range off of AMD RTC registers
176 default CONFIG_LB_CKS_RANGE_START=49
177 default CONFIG_LB_CKS_RANGE_END=122
178 default CONFIG_LB_CKS_LOC=123
181 ## Build code for SMP support
182 ## Only worry about 2 micro processors
185 default CONFIG_MAX_PHYSICAL_CPUS=2
186 default CONFIG_MAX_CPUS=4 * CONFIG_MAX_PHYSICAL_CPUS
187 default CONFIG_LOGICAL_CPUS=1
189 #default CONFIG_SERIAL_CPU_INIT=0
191 default CONFIG_ENABLE_APIC_EXT_ID=1
192 default CONFIG_APIC_ID_OFFSET=0x00
193 default CONFIG_LIFT_BSP_APIC_ID=1
195 #memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
197 #default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
199 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
201 #default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
203 #make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
204 #default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
207 default CONFIG_CONSOLE_VGA=1
208 default CONFIG_PCI_ROM_RUN=1
210 #default CONFIG_USBDEBUG_DIRECT=1
212 #HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
213 default CONFIG_HT_CHAIN_UNITID_BASE=1
215 #real SB Unit ID, default is 0x20, mean dont touch it at last
216 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
218 #make the SB HT chain on bus 0, default is not (0)
219 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
221 #only offset for SB chain?, default is yes(1)
222 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
224 #allow capable device use that above 4G
225 #default CONFIG_PCI_64BIT_PREF_MEM=1
228 ## enable CACHE_AS_RAM specifics
230 default CONFIG_USE_DCACHE_RAM=1
231 default CONFIG_DCACHE_RAM_BASE=0xc4000
232 default CONFIG_DCACHE_RAM_SIZE=0x0c000
233 default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
234 default CONFIG_USE_INIT=0
236 default CONFIG_MEM_TRAIN_SEQ=2
237 default CONFIG_WAIT_BEFORE_CPUS_INIT=0
238 default CONFIG_AMDMCT = 1
241 ## Build code to setup a generic IOAPIC
243 default CONFIG_IOAPIC=1
246 ## Clean up the motherboard id strings
248 default CONFIG_MAINBOARD_PART_NUMBER="S2912 (Fam10)"
249 default CONFIG_MAINBOARD_VENDOR="Tyan"
250 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
251 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2912
254 ## Set microcode patch file name
256 ## Barcelona rev DR-Ax: "mc_patch_01000020.h"
257 ## Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
258 ## Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
259 ## Shanghai rev DA-C2: "mc_patch_0100009f.h"
261 default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
264 ### coreboot layout values
267 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
268 default CONFIG_ROM_IMAGE_SIZE = (128*1024) - CONFIG_FAILOVER_SIZE
271 ## Use a small 8K stack
273 default CONFIG_STACK_SIZE=0x2000
276 ## Use a small 32K heap
278 default CONFIG_HEAP_SIZE=0xc0000
281 ## Only use the option table in a normal image
283 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
286 ## Coreboot C code runs at this location in RAM
288 default CONFIG_RAMBASE=0x00200000
291 ## Load the payload from the ROM
293 default CONFIG_ROM_PAYLOAD = 1
295 #default CONFIG_COMPRESSED_PAYLOAD = 1
298 ### Defaults of options that you may want to override in the target config file
302 ## The default compiler
304 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
308 ## Disable the gdb stub by default
310 default CONFIG_GDB_STUB=0
313 ## The Serial Console
315 default CONFIG_USE_PRINTK_IN_CAR=1
317 # To Enable the Serial Console
318 default CONFIG_CONSOLE_SERIAL8250=1
320 ## Select the serial console baud rate
321 default CONFIG_TTYS0_BAUD=115200
322 #default CONFIG_TTYS0_BAUD=57600
323 #default CONFIG_TTYS0_BAUD=38400
324 #default CONFIG_TTYS0_BAUD=19200
325 #default CONFIG_TTYS0_BAUD=9600
326 #default CONFIG_TTYS0_BAUD=4800
327 #default CONFIG_TTYS0_BAUD=2400
328 #default CONFIG_TTYS0_BAUD=1200
330 # Select the serial console base port
331 default CONFIG_TTYS0_BASE=0x3f8
333 # Select the serial protocol
334 # This defaults to 8 data bits, 1 stop bit, and no parity
335 default CONFIG_TTYS0_LCS=0x3
338 ### Select the coreboot loglevel
340 ## EMERG 1 system is unusable
341 ## ALERT 2 action must be taken immediately
342 ## CRIT 3 critical conditions
343 ## ERR 4 error conditions
344 ## WARNING 5 warning conditions
345 ## NOTICE 6 normal but significant condition
346 ## INFO 7 informational
347 ## CONFIG_DEBUG 8 debug-level messages
348 ## SPEW 9 Way too many details
350 ## Request this level of debugging output
351 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
352 ## At a maximum only compile in this level of debugging
353 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
356 ## Select power on after power fail setting
357 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"