Thanks to Myles' patch adding support for include statements,
[coreboot.git] / src / mainboard / tyan / s2912_fam10 / Config.lb
1 ##
2 ## This file is part of the coreboot project.
3 ##
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
6 ##
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
11 ##
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 ## GNU General Public License for more details.
16 ##
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
20 ##
21
22 include /config/failovercalculation.lb
23
24 arch i386 end
25
26 ##
27 ## Build the objects we have code for in this directory.
28 ##
29
30 driver mainboard.o
31 #needed by irq_tables and mptable and acpi_tables
32 object get_bus_conf.o
33
34 if HAVE_MP_TABLE object mptable.o end
35 if HAVE_PIRQ_TABLE object irq_tables.o end
36 #object reset.o
37
38         if CONFIG_USE_INIT
39                 makerule ./cache_as_ram_auto.o
40                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
41                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
42                 end
43         else
44                 makerule ./cache_as_ram_auto.inc
45                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
46                         action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
47                         action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
48                         action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
49                 end
50         end
51
52 if USE_FAILOVER_IMAGE
53 else
54     if CONFIG_AP_CODE_IN_CAR
55         makerule ./apc_auto.o
56                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
57                 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
58         end
59         ldscript /arch/i386/init/ldscript_apc.lb
60     end
61 end
62
63
64 ##
65 ## Build our 16 bit and 32 bit coreboot entry code
66 ##
67 if HAVE_FAILOVER_BOOT
68     if USE_FAILOVER_IMAGE
69         mainboardinit cpu/x86/16bit/entry16.inc
70         ldscript /cpu/x86/16bit/entry16.lds
71     end
72 else
73     if USE_FALLBACK_IMAGE
74         mainboardinit cpu/x86/16bit/entry16.inc
75         ldscript /cpu/x86/16bit/entry16.lds
76     end
77 end
78
79 mainboardinit cpu/x86/32bit/entry32.inc
80
81         if CONFIG_USE_INIT
82                 ldscript /cpu/x86/32bit/entry32.lds
83         end
84
85         if CONFIG_USE_INIT
86                 ldscript /cpu/amd/car/cache_as_ram.lds
87         end
88
89 ##
90 ## Build our reset vector (This is where coreboot is entered)
91 ##
92 if HAVE_FAILOVER_BOOT
93     if USE_FAILOVER_IMAGE
94         mainboardinit cpu/x86/16bit/reset16.inc
95         ldscript /cpu/x86/16bit/reset16.lds
96     else
97         mainboardinit cpu/x86/32bit/reset32.inc
98         ldscript /cpu/x86/32bit/reset32.lds
99     end
100 else
101     if USE_FALLBACK_IMAGE
102         mainboardinit cpu/x86/16bit/reset16.inc
103         ldscript /cpu/x86/16bit/reset16.lds
104     else
105         mainboardinit cpu/x86/32bit/reset32.inc
106         ldscript /cpu/x86/32bit/reset32.lds
107     end
108 end
109
110 ##
111 ## Include an id string (For safe flashing)
112 ##
113 mainboardinit southbridge/nvidia/mcp55/id.inc
114 ldscript /southbridge/nvidia/mcp55/id.lds
115
116 ##
117 ## ROMSTRAP table for MCP55
118 ##
119 if HAVE_FAILOVER_BOOT
120     if USE_FAILOVER_IMAGE
121         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
122         ldscript /southbridge/nvidia/mcp55/romstrap.lds
123     end
124 else
125     if USE_FALLBACK_IMAGE
126         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
127         ldscript /southbridge/nvidia/mcp55/romstrap.lds
128     end
129 end
130
131         ##
132         ## Setup Cache-As-Ram
133         ##
134         mainboardinit cpu/amd/car/cache_as_ram.inc
135
136 ###
137 ### This is the early phase of coreboot startup
138 ### Things are delicate and we test to see if we should
139 ### failover to another image.
140 ###
141 if HAVE_FAILOVER_BOOT
142     if USE_FAILOVER_IMAGE
143                 ldscript /arch/i386/lib/failover_failover.lds
144     end
145 else
146     if USE_FALLBACK_IMAGE
147                 ldscript /arch/i386/lib/failover.lds
148     end
149 end
150
151 ##
152 ## Setup RAM
153 ##
154         if CONFIG_USE_INIT
155                 initobject cache_as_ram_auto.o
156         else
157                 mainboardinit ./cache_as_ram_auto.inc
158         end
159
160 ##
161 ## Include the secondary Configuration files
162 ##
163 config chip.h
164
165 dir /southbridge/nvidia/mcp55
166
167 chip northbridge/amd/amdfam10/root_complex
168         device apic_cluster 0 on
169                 chip cpu/amd/socket_F_1207
170                         device apic 0 on end
171                 end
172         end
173         device pci_domain 0 on
174                 chip northbridge/amd/amdfam10 #mc0
175                         device pci 18.0 on end
176                         device pci 18.0 on end
177                         device pci 18.0 on
178                                 #  SB on link 2.0.
179                                 chip southbridge/nvidia/mcp55
180                                         device pci 0.0 on end   # HT
181                                         device pci 1.0 on # LPC
182                                                 chip superio/winbond/w83627hf
183                                                         device pnp 2e.0 off #  Floppy
184                                                                 io 0x60 = 0x3f0
185                                                                 irq 0x70 = 6
186                                                                 drq 0x74 = 2
187                                                         end
188                                                         device pnp 2e.1 off #  Parallel Port
189                                                                 io 0x60 = 0x378
190                                                                 irq 0x70 = 7
191                                                         end
192                                                         device pnp 2e.2 on #  Com1
193                                                                 io 0x60 = 0x3f8
194                                                                 irq 0x70 = 4
195                                                         end
196                                                         device pnp 2e.3 on #  Com2
197                                                                 io 0x60 = 0x2f8
198                                                                 irq 0x70 = 3
199                                                         end
200                                                         device pnp 2e.5 on #  Keyboard
201                                                                 io 0x60 = 0x60
202                                                                 io 0x62 = 0x64
203                                                                 irq 0x70 = 1
204                                                                 irq 0x72 = 12
205                                                         end
206                                                         device pnp 2e.6 off  # SFI
207                                                                 io 0x62 = 0x100
208                                                         end
209                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
210                                                                 io 0x60 = 0x220
211                                                                 io 0x62 = 0x300
212                                                                 irq 0x70 = 9
213                                                         end
214                                                         device pnp 2e.8 off end #  WDTO_PLED
215                                                         device pnp 2e.9 off end #  GPIO_SUSLED
216                                                         device pnp 2e.a off end #  ACPI
217                                                         device pnp 2e.b on #  HW Monitor
218                                                                 io 0x60 = 0x290
219                                                                 irq 0x70 = 5
220                                                         end
221                                                 end
222                                         end
223                                         device pci 1.1 on # SM 0
224                                                 chip drivers/generic/generic #dimm 0-0-0
225                                                         device i2c 50 on end
226                                                 end
227                                                 chip drivers/generic/generic #dimm 0-0-1
228                                                         device i2c 51 on end
229                                                 end
230                                                 chip drivers/generic/generic #dimm 0-1-0
231                                                         device i2c 52 on end
232                                                 end
233                                                 chip drivers/generic/generic #dimm 0-1-1
234                                                         device i2c 53 on end
235                                                 end
236                                                 chip drivers/generic/generic #dimm 1-0-0
237                                                         device i2c 54 on end
238                                                 end
239                                                 chip drivers/generic/generic #dimm 1-0-1
240                                                         device i2c 55 on end
241                                                 end
242                                                 chip drivers/generic/generic #dimm 1-1-0
243                                                         device i2c 56 on end
244                                                 end
245                                                 chip drivers/generic/generic #dimm 1-1-1
246                                                         device i2c 57 on end
247                                                 end
248                                         end # SM
249                                         device pci 1.1 on # SM 1
250 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
251 #                                               chip drivers/generic/generic #PCIXA Slot1
252 #                                                       device i2c 50 on end
253 #                                               end
254 #                                               chip drivers/generic/generic #PCIXB Slot1
255 #                                                       device i2c 51 on end
256 #                                               end
257 #                                               chip drivers/generic/generic #PCIXB Slot2
258 #                                                       device i2c 52 on end
259 #                                               end
260 #                                               chip drivers/generic/generic #PCI Slot1
261 #                                                       device i2c 53 on end
262 #                                               end
263 #                                               chip drivers/generic/generic #Master MCP55 PCI-E
264 #                                                       device i2c 54 on end
265 #                                               end
266 #                                               chip drivers/generic/generic #Slave MCP55 PCI-E
267 #                                                       device i2c 55 on end
268 #                                               end
269                                                 chip drivers/generic/generic #MAC EEPROM
270                                                         device i2c 51 on end
271                                                 end
272
273                                         end # SM
274                                         device pci 2.0 on end # USB 1.1
275                                         device pci 2.1 on end # USB 2
276                                         device pci 4.0 on end # IDE
277                                         device pci 5.0 on end # SATA 0
278                                         device pci 5.1 on end # SATA 1
279                                         device pci 5.2 on end # SATA 2
280                                         device pci 6.0 on
281                                                 chip drivers/pci/onboard
282                                                         device pci 4.0 on end
283                                                         register "rom_address" = "0xfff00000"
284                                                 end
285                                         end # PCI
286                                         device pci 6.1 off end # AZA
287                                         device pci 8.0 on end # NIC
288                                         device pci 9.0 on end # NIC
289                                         device pci a.0 on end # PCI E 5
290                                         device pci b.0 off end # PCI E 4
291                                         device pci c.0 off end # PCI E 3
292                                         device pci d.0 on end # PCI E 2
293                                         device pci e.0 off end # PCI E 1
294                                         device pci f.0 on end # PCI E 0
295                                         register "ide0_enable" = "1"
296                                         register "sata0_enable" = "1"
297                                         register "sata1_enable" = "1"
298                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
299                                         register "mac_eeprom_addr" = "0x51"
300                                 end
301                         end #  device pci 18.0
302                         device pci 18.1 on end
303                         device pci 18.2 on end
304                         device pci 18.3 on end
305                         device pci 18.4 on end
306                 end # mc0
307
308         end # PCI domain
309
310 #       chip drivers/generic/debug
311 #               device pnp 0.0 off end # chip name
312 #               device pnp 0.1 on end # pci_regs_all
313 #               device pnp 0.2 on end # mem
314 #               device pnp 0.3 off end # cpuid
315 #               device pnp 0.4 on end # smbus_regs_all
316 #               device pnp 0.5 off end # dual core msr
317 #               device pnp 0.6 off end # cache size
318 #               device pnp 0.7 off end # tsc
319 #               device pnp 0.8 off  end # io
320 #               device pnp 0.9 off end # io
321 #       end
322 end #root_complex