2 ## This file is part of the coreboot project.
4 ## Copyright (C) 2007 AMD
5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
7 ## This program is free software; you can redistribute it and/or modify
8 ## it under the terms of the GNU General Public License as published by
9 ## the Free Software Foundation; either version 2 of the License, or
10 ## (at your option) any later version.
12 ## This program is distributed in the hope that it will be useful,
13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ## GNU General Public License for more details.
17 ## You should have received a copy of the GNU General Public License
18 ## along with this program; if not, write to the Free Software
19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 include /config/failovercalculation.lb
27 ## Build the objects we have code for in this directory.
31 #needed by irq_tables and mptable and acpi_tables
34 if HAVE_MP_TABLE object mptable.o end
35 if HAVE_PIRQ_TABLE object irq_tables.o end
39 makerule ./cache_as_ram_auto.o
40 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
41 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
44 makerule ./cache_as_ram_auto.inc
45 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
46 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
47 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
48 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
54 if CONFIG_AP_CODE_IN_CAR
56 depends "$(MAINBOARD)/apc_auto.c option_table.h"
57 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c $(MAINBOARD)/apc_auto.c -o $@"
59 ldscript /arch/i386/init/ldscript_apc.lb
65 ## Build our 16 bit and 32 bit coreboot entry code
69 mainboardinit cpu/x86/16bit/entry16.inc
70 ldscript /cpu/x86/16bit/entry16.lds
74 mainboardinit cpu/x86/16bit/entry16.inc
75 ldscript /cpu/x86/16bit/entry16.lds
79 mainboardinit cpu/x86/32bit/entry32.inc
82 ldscript /cpu/x86/32bit/entry32.lds
86 ldscript /cpu/amd/car/cache_as_ram.lds
90 ## Build our reset vector (This is where coreboot is entered)
94 mainboardinit cpu/x86/16bit/reset16.inc
95 ldscript /cpu/x86/16bit/reset16.lds
97 mainboardinit cpu/x86/32bit/reset32.inc
98 ldscript /cpu/x86/32bit/reset32.lds
101 if USE_FALLBACK_IMAGE
102 mainboardinit cpu/x86/16bit/reset16.inc
103 ldscript /cpu/x86/16bit/reset16.lds
105 mainboardinit cpu/x86/32bit/reset32.inc
106 ldscript /cpu/x86/32bit/reset32.lds
111 ## Include an id string (For safe flashing)
113 mainboardinit southbridge/nvidia/mcp55/id.inc
114 ldscript /southbridge/nvidia/mcp55/id.lds
117 ## ROMSTRAP table for MCP55
119 if HAVE_FAILOVER_BOOT
120 if USE_FAILOVER_IMAGE
121 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
122 ldscript /southbridge/nvidia/mcp55/romstrap.lds
125 if USE_FALLBACK_IMAGE
126 mainboardinit southbridge/nvidia/mcp55/romstrap.inc
127 ldscript /southbridge/nvidia/mcp55/romstrap.lds
132 ## Setup Cache-As-Ram
134 mainboardinit cpu/amd/car/cache_as_ram.inc
137 ### This is the early phase of coreboot startup
138 ### Things are delicate and we test to see if we should
139 ### failover to another image.
141 if HAVE_FAILOVER_BOOT
142 if USE_FAILOVER_IMAGE
143 ldscript /arch/i386/lib/failover_failover.lds
146 if USE_FALLBACK_IMAGE
147 ldscript /arch/i386/lib/failover.lds
155 initobject cache_as_ram_auto.o
157 mainboardinit ./cache_as_ram_auto.inc
161 ## Include the secondary Configuration files
165 dir /southbridge/nvidia/mcp55
167 chip northbridge/amd/amdfam10/root_complex
168 device apic_cluster 0 on
169 chip cpu/amd/socket_F_1207
173 device pci_domain 0 on
174 chip northbridge/amd/amdfam10 #mc0
175 device pci 18.0 on end
176 device pci 18.0 on end
179 chip southbridge/nvidia/mcp55
180 device pci 0.0 on end # HT
181 device pci 1.0 on # LPC
182 chip superio/winbond/w83627hf
183 device pnp 2e.0 off # Floppy
188 device pnp 2e.1 off # Parallel Port
192 device pnp 2e.2 on # Com1
196 device pnp 2e.3 on # Com2
200 device pnp 2e.5 on # Keyboard
206 device pnp 2e.6 off # SFI
209 device pnp 2e.7 off # GPIO_GAME_MIDI
214 device pnp 2e.8 off end # WDTO_PLED
215 device pnp 2e.9 off end # GPIO_SUSLED
216 device pnp 2e.a off end # ACPI
217 device pnp 2e.b on # HW Monitor
223 device pci 1.1 on # SM 0
224 chip drivers/generic/generic #dimm 0-0-0
227 chip drivers/generic/generic #dimm 0-0-1
230 chip drivers/generic/generic #dimm 0-1-0
233 chip drivers/generic/generic #dimm 0-1-1
236 chip drivers/generic/generic #dimm 1-0-0
239 chip drivers/generic/generic #dimm 1-0-1
242 chip drivers/generic/generic #dimm 1-1-0
245 chip drivers/generic/generic #dimm 1-1-1
249 device pci 1.1 on # SM 1
250 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
251 # chip drivers/generic/generic #PCIXA Slot1
252 # device i2c 50 on end
254 # chip drivers/generic/generic #PCIXB Slot1
255 # device i2c 51 on end
257 # chip drivers/generic/generic #PCIXB Slot2
258 # device i2c 52 on end
260 # chip drivers/generic/generic #PCI Slot1
261 # device i2c 53 on end
263 # chip drivers/generic/generic #Master MCP55 PCI-E
264 # device i2c 54 on end
266 # chip drivers/generic/generic #Slave MCP55 PCI-E
267 # device i2c 55 on end
269 chip drivers/generic/generic #MAC EEPROM
274 device pci 2.0 on end # USB 1.1
275 device pci 2.1 on end # USB 2
276 device pci 4.0 on end # IDE
277 device pci 5.0 on end # SATA 0
278 device pci 5.1 on end # SATA 1
279 device pci 5.2 on end # SATA 2
281 chip drivers/pci/onboard
282 device pci 4.0 on end
283 register "rom_address" = "0xfff00000"
286 device pci 6.1 off end # AZA
287 device pci 8.0 on end # NIC
288 device pci 9.0 on end # NIC
289 device pci a.0 on end # PCI E 5
290 device pci b.0 off end # PCI E 4
291 device pci c.0 off end # PCI E 3
292 device pci d.0 on end # PCI E 2
293 device pci e.0 off end # PCI E 1
294 device pci f.0 on end # PCI E 0
295 register "ide0_enable" = "1"
296 register "sata0_enable" = "1"
297 register "sata1_enable" = "1"
298 register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
299 register "mac_eeprom_addr" = "0x51"
301 end # device pci 18.0
302 device pci 18.1 on end
303 device pci 18.2 on end
304 device pci 18.3 on end
305 device pci 18.4 on end
310 # chip drivers/generic/debug
311 # device pnp 0.0 off end # chip name
312 # device pnp 0.1 on end # pci_regs_all
313 # device pnp 0.2 on end # mem
314 # device pnp 0.3 off end # cpuid
315 # device pnp 0.4 on end # smbus_regs_all
316 # device pnp 0.5 off end # dual core msr
317 # device pnp 0.6 off end # cache size
318 # device pnp 0.7 off end # tsc
319 # device pnp 0.8 off end # io
320 # device pnp 0.9 off end # io