src/mainboard/tyan/s2912_fam10/Config.lb

   1 ##
   2 ## This file is part of the coreboot project.
   3 ##
   4 ## Copyright (C) 2007 AMD
   5 ## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
   6 ##
   7 ## This program is free software; you can redistribute it and/or modify
   8 ## it under the terms of the GNU General Public License as published by
   9 ## the Free Software Foundation; either version 2 of the License, or
  10 ## (at your option) any later version.
  11 ##
  12 ## This program is distributed in the hope that it will be useful,
  13 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 ## GNU General Public License for more details.
  16 ##
  17 ## You should have received a copy of the GNU General Public License
  18 ## along with this program; if not, write to the Free Software
  19 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  20 ##
  21
  22 ##
  23 ## Compute the location and size of where this firmware image
  24 ## (coreboot plus bootloader) will live in the boot rom chip.
  25 ##
  26 if USE_FAILOVER_IMAGE
  27         default ROM_SECTION_SIZE   = FAILOVER_SIZE
  28         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
  29 else
  30     if USE_FALLBACK_IMAGE
  31         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  32         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  33     else
  34         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  35         default ROM_SECTION_OFFSET = 0
  36     end
  37 end
  38
  39 ##
  40 ## Compute the start location and size size of
  41 ## The coreboot bootloader.
  42 ##
  43 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  44 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  45
  46 ##
  47 ## Compute where this copy of coreboot will start in the boot rom
  48 ##
  49 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  50
  51 ##
  52 ## Compute a range of ROM that can cached to speed up coreboot,
  53 ## execution speed.
  54 ##
  55 ## XIP_ROM_SIZE must be a power of 2.
  56 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  57 ##
  58 default XIP_ROM_SIZE=65536
  59
  60 if USE_FAILOVER_IMAGE
  61         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  62 else
  63     if USE_FALLBACK_IMAGE
  64         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  65     else
  66         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  67     end
  68 end
  69
  70 arch i386 end
  71
  72 ##
  73 ## Build the objects we have code for in this directory.
  74 ##
  75
  76 driver mainboard.o
  77 #needed by irq_tables and mptable and acpi_tables
  78 object get_bus_conf.o
  79
  80 if HAVE_MP_TABLE object mptable.o end
  81 if HAVE_PIRQ_TABLE object irq_tables.o end
  82 #object reset.o
  83
  84 if USE_DCACHE_RAM
  85         makedefine CACHE_AS_RAM_AUTO_C:=cache_as_ram_auto.c
  86
  87         if CONFIG_USE_INIT
  88                 makerule ./cache_as_ram_auto.o
  89                         depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
  90                         action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
  91                 end
  92         else
  93                 makerule ./cache_as_ram_auto.inc
  94                         depends "$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) option_table.h"
  95                         action "$(CC) -I$(TOP)/src -I. $(CFLAGS) $(CPPFLAGS) $(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  96                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  97                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  98                 end
  99         end
 100
 101 end
 102
 103 if USE_FAILOVER_IMAGE
 104 else
 105     if CONFIG_AP_CODE_IN_CAR
 106         makerule ./apc_auto.o
 107                 depends "$(MAINBOARD)/apc_auto.c option_table.h"
 108                 action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
 109         end
 110         ldscript /arch/i386/init/ldscript_apc.lb
 111     end
 112 end
 113
 114
 115 ##
 116 ## Build our 16 bit and 32 bit coreboot entry code
 117 ##
 118 if HAVE_FAILOVER_BOOT
 119     if USE_FAILOVER_IMAGE
 120         mainboardinit cpu/x86/16bit/entry16.inc
 121         ldscript /cpu/x86/16bit/entry16.lds
 122     end
 123 else
 124     if USE_FALLBACK_IMAGE
 125         mainboardinit cpu/x86/16bit/entry16.inc
 126         ldscript /cpu/x86/16bit/entry16.lds
 127     end
 128 end
 129
 130 mainboardinit cpu/x86/32bit/entry32.inc
 131
 132 if USE_DCACHE_RAM
 133         if CONFIG_USE_INIT
 134                 ldscript /cpu/x86/32bit/entry32.lds
 135         end
 136
 137         if CONFIG_USE_INIT
 138                 ldscript /cpu/amd/car/cache_as_ram.lds
 139         end
 140 end
 141
 142
 143 ##
 144 ## Build our reset vector (This is where coreboot is entered)
 145 ##
 146 if HAVE_FAILOVER_BOOT
 147     if USE_FAILOVER_IMAGE
 148         mainboardinit cpu/x86/16bit/reset16.inc
 149         ldscript /cpu/x86/16bit/reset16.lds
 150     else
 151         mainboardinit cpu/x86/32bit/reset32.inc
 152         ldscript /cpu/x86/32bit/reset32.lds
 153     end
 154 else
 155     if USE_FALLBACK_IMAGE
 156         mainboardinit cpu/x86/16bit/reset16.inc
 157         ldscript /cpu/x86/16bit/reset16.lds
 158     else
 159         mainboardinit cpu/x86/32bit/reset32.inc
 160         ldscript /cpu/x86/32bit/reset32.lds
 161     end
 162 end
 163
 164 ##
 165 ## Include an id string (For safe flashing)
 166 ##
 167 mainboardinit southbridge/nvidia/mcp55/id.inc
 168 ldscript /southbridge/nvidia/mcp55/id.lds
 169
 170 ##
 171 ## ROMSTRAP table for MCP55
 172 ##
 173 if HAVE_FAILOVER_BOOT
 174     if USE_FAILOVER_IMAGE
 175         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 176         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 177     end
 178 else
 179     if USE_FALLBACK_IMAGE
 180         mainboardinit southbridge/nvidia/mcp55/romstrap.inc
 181         ldscript /southbridge/nvidia/mcp55/romstrap.lds
 182     end
 183 end
 184
 185 if USE_DCACHE_RAM
 186         ##
 187         ## Setup Cache-As-Ram
 188         ##
 189         mainboardinit cpu/amd/car/cache_as_ram.inc
 190 end
 191
 192 ###
 193 ### This is the early phase of coreboot startup
 194 ### Things are delicate and we test to see if we should
 195 ### failover to another image.
 196 ###
 197 if HAVE_FAILOVER_BOOT
 198     if USE_FAILOVER_IMAGE
 199         if USE_DCACHE_RAM
 200                 ldscript /arch/i386/lib/failover_failover.lds
 201         end
 202     end
 203 else
 204     if USE_FALLBACK_IMAGE
 205         if USE_DCACHE_RAM
 206                 ldscript /arch/i386/lib/failover.lds
 207         end
 208     end
 209 end
 210
 211 ##
 212 ## Setup RAM
 213 ##
 214 if USE_DCACHE_RAM
 215
 216         if CONFIG_USE_INIT
 217                 initobject cache_as_ram_auto.o
 218         else
 219                 mainboardinit ./cache_as_ram_auto.inc
 220         end
 221 end
 222
 223 ##
 224 ## Include the secondary Configuration files
 225 ##
 226 if CONFIG_CHIP_NAME
 227         config chip.h
 228 end
 229
 230 dir /southbridge/nvidia/mcp55
 231
 232 chip northbridge/amd/amdfam10/root_complex
 233         device apic_cluster 0 on
 234                 chip cpu/amd/socket_F_1207
 235                         device apic 0 on end
 236                 end
 237         end
 238         device pci_domain 0 on
 239                 chip northbridge/amd/amdfam10 #mc0
 240                         device pci 18.0 on end
 241                         device pci 18.0 on end
 242                         device pci 18.0 on
 243                                 #  SB on link 2.0.
 244                                 chip southbridge/nvidia/mcp55
 245                                         device pci 0.0 on end   # HT
 246                                         device pci 1.0 on # LPC
 247                                                 chip superio/winbond/w83627hf
 248                                                         device pnp 2e.0 off #  Floppy
 249                                                                 io 0x60 = 0x3f0
 250                                                                 irq 0x70 = 6
 251                                                                 drq 0x74 = 2
 252                                                         end
 253                                                         device pnp 2e.1 off #  Parallel Port
 254                                                                 io 0x60 = 0x378
 255                                                                 irq 0x70 = 7
 256                                                         end
 257                                                         device pnp 2e.2 on #  Com1
 258                                                                 io 0x60 = 0x3f8
 259                                                                 irq 0x70 = 4
 260                                                         end
 261                                                         device pnp 2e.3 on #  Com2
 262                                                                 io 0x60 = 0x2f8
 263                                                                 irq 0x70 = 3
 264                                                         end
 265                                                         device pnp 2e.5 on #  Keyboard
 266                                                                 io 0x60 = 0x60
 267                                                                 io 0x62 = 0x64
 268                                                                 irq 0x70 = 1
 269                                                                 irq 0x72 = 12
 270                                                         end
 271                                                         device pnp 2e.6 off  # SFI
 272                                                                 io 0x62 = 0x100
 273                                                         end
 274                                                         device pnp 2e.7 off #  GPIO_GAME_MIDI
 275                                                                 io 0x60 = 0x220
 276                                                                 io 0x62 = 0x300
 277                                                                 irq 0x70 = 9
 278                                                         end
 279                                                         device pnp 2e.8 off end #  WDTO_PLED
 280                                                         device pnp 2e.9 off end #  GPIO_SUSLED
 281                                                         device pnp 2e.a off end #  ACPI
 282                                                         device pnp 2e.b on #  HW Monitor
 283                                                                 io 0x60 = 0x290
 284                                                                 irq 0x70 = 5
 285                                                         end
 286                                                 end
 287                                         end
 288                                         device pci 1.1 on # SM 0
 289                                                 chip drivers/generic/generic #dimm 0-0-0
 290                                                         device i2c 50 on end
 291                                                 end
 292                                                 chip drivers/generic/generic #dimm 0-0-1
 293                                                         device i2c 51 on end
 294                                                 end
 295                                                 chip drivers/generic/generic #dimm 0-1-0
 296                                                         device i2c 52 on end
 297                                                 end
 298                                                 chip drivers/generic/generic #dimm 0-1-1
 299                                                         device i2c 53 on end
 300                                                 end
 301                                                 chip drivers/generic/generic #dimm 1-0-0
 302                                                         device i2c 54 on end
 303                                                 end
 304                                                 chip drivers/generic/generic #dimm 1-0-1
 305                                                         device i2c 55 on end
 306                                                 end
 307                                                 chip drivers/generic/generic #dimm 1-1-0
 308                                                         device i2c 56 on end
 309                                                 end
 310                                                 chip drivers/generic/generic #dimm 1-1-1
 311                                                         device i2c 57 on end
 312                                                 end
 313                                         end # SM
 314                                         device pci 1.1 on # SM 1
 315 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 316 #                                                chip drivers/generic/generic #PCIXA Slot1
 317 #                                                        device i2c 50 on end
 318 #                                                end
 319 #                                                chip drivers/generic/generic #PCIXB Slot1
 320 #                                                        device i2c 51 on end
 321 #                                                end
 322 #                                                chip drivers/generic/generic #PCIXB Slot2
 323 #                                                        device i2c 52 on end
 324 #                                                end
 325 #                                                chip drivers/generic/generic #PCI Slot1
 326 #                                                        device i2c 53 on end
 327 #                                                end
 328 #                                                chip drivers/generic/generic #Master MCP55 PCI-E
 329 #                                                        device i2c 54 on end
 330 #                                                end
 331 #                                                chip drivers/generic/generic #Slave MCP55 PCI-E
 332 #                                                        device i2c 55 on end
 333 #                                                end
 334                                                 chip drivers/generic/generic #MAC EEPROM
 335                                                         device i2c 51 on end
 336                                                 end
 337
 338                                         end # SM
 339                                         device pci 2.0 on end # USB 1.1
 340                                         device pci 2.1 on end # USB 2
 341                                         device pci 4.0 on end # IDE
 342                                         device pci 5.0 on end # SATA 0
 343                                         device pci 5.1 on end # SATA 1
 344                                         device pci 5.2 on end # SATA 2
 345                                         device pci 6.0 on
 346                                                 chip drivers/pci/onboard
 347                                                         device pci 4.0 on end
 348                                                         register "rom_address" = "0xfff80000"
 349                                                 end
 350                                          end # PCI
 351                                         device pci 6.1 off end # AZA
 352                                         device pci 8.0 on end # NIC
 353                                         device pci 9.0 on end # NIC
 354                                         device pci a.0 on end # PCI E 5
 355                                         device pci b.0 off end # PCI E 4
 356                                         device pci c.0 off end # PCI E 3
 357                                         device pci d.0 on end # PCI E 2
 358                                         device pci e.0 off end # PCI E 1
 359                                         device pci f.0 on end # PCI E 0
 360                                         register "ide0_enable" = "1"
 361                                         register "sata0_enable" = "1"
 362                                         register "sata1_enable" = "1"
 363                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 364                                         register "mac_eeprom_addr" = "0x51"
 365                                 end
 366                         end #  device pci 18.0
 367                         device pci 18.1 on end
 368                         device pci 18.2 on end
 369                         device pci 18.3 on end
 370                         device pci 18.4 on end
 371                 end # mc0
 372
 373         end # PCI domain
 374
 375 #       chip drivers/generic/debug
 376 #               device pnp 0.0 off end # chip name
 377 #                device pnp 0.1 on end # pci_regs_all
 378 #                device pnp 0.2 on end # mem
 379 #                device pnp 0.3 off end # cpuid
 380 #                device pnp 0.4 on end # smbus_regs_all
 381 #                device pnp 0.5 off end # dual core msr
 382 #                device pnp 0.6 off end # cache size
 383 #               device pnp 0.7 off end # tsc
 384 #                device pnp 0.8 off  end # io
 385 #                device pnp 0.9 off end # io
 386 #       end
 387 end #root_complex