src/mainboard/tyan/s2895/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define K8_ALLOCATE_IO_RANGE 1
   5
   6 #define QRANK_DIMM_SUPPORT 1
   7
   8 #if CONFIG_LOGICAL_CPUS==1
   9 #define SET_NB_CFG_54 1
  10 #endif
  11
  12 #include <stdint.h>
  13 #include <string.h>
  14 #include <device/pci_def.h>
  15 #include <arch/io.h>
  16 #include <device/pnp_def.h>
  17 #include <arch/romcc_io.h>
  18 #include <cpu/x86/lapic.h>
  19 #include "option_table.h"
  20 #include "pc80/mc146818rtc_early.c"
  21
  22 #if CONFIG_USE_FAILOVER_IMAGE==0
  23 #include "pc80/serial.c"
  24 #include "arch/i386/lib/console.c"
  25 #include "lib/ramtest.c"
  26
  27 #include <cpu/amd/model_fxx_rev.h>
  28
  29 #include "northbridge/amd/amdk8/incoherent_ht.c"
  30 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  31 #include "northbridge/amd/amdk8/raminit.h"
  32 #include "cpu/amd/model_fxx/apic_timer.c"
  33 #include "lib/delay.c"
  34
  35 #endif
  36
  37 #include "cpu/x86/lapic/boot_cpu.c"
  38 #include "northbridge/amd/amdk8/reset_test.c"
  39 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  40 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  41 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  42
  43 #define SUPERIO_GPIO_IO_BASE 0x400
  44
  45 #if CONFIG_USE_FAILOVER_IMAGE==0
  46
  47 #include "cpu/x86/bist.h"
  48
  49 #include "northbridge/amd/amdk8/debug.c"
  50
  51 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  52
  53 #include "northbridge/amd/amdk8/setup_resource_map.c"
  54
  55 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  56
  57 static void memreset_setup(void)
  58 {
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 static void sio_gpio_setup(void){
  66
  67         unsigned value;
  68
  69         /*Enable onboard scsi*/
  70         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  71         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  72         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  73
  74 }
  75
  76 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  77 {
  78         /* nothing to do */
  79 }
  80
  81 static inline int spd_read_byte(unsigned device, unsigned address)
  82 {
  83         return smbus_read_byte(device, address);
  84 }
  85
  86 #include "northbridge/amd/amdk8/raminit.c"
  87 #include "northbridge/amd/amdk8/coherent_ht.c"
  88 #include "lib/generic_sdram.c"
  89
  90  /* tyan does not want the default */
  91 #include "resourcemap.c"
  92
  93 #include "cpu/amd/dualcore/dualcore.c"
  94
  95 #define CK804_NUM 2
  96 #define CK804_USE_NIC 1
  97 #define CK804_USE_ACI 1
  98
  99 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 100
 101 //set GPIO to input mode
 102 #define CK804_MB_SETUP \
 103         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 104         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 105         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 106         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 107         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 108         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 109
 110 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 111
 112 #include "cpu/amd/car/copy_and_run.c"
 113 #include "cpu/amd/car/post_cache_as_ram.c"
 114
 115 #include "cpu/amd/model_fxx/init_cpus.c"
 116
 117 #endif
 118
 119 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 120
 121 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 122 #include "northbridge/amd/amdk8/early_ht.c"
 123
 124 static void sio_setup(void)
 125 {
 126
 127         unsigned value;
 128         uint32_t dword;
 129         uint8_t byte;
 130
 131         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 132
 133         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 134         byte |= 0x20;
 135         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 136
 137         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 138         dword |= (1<<29)|(1<<0);
 139         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 140
 141         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 142         dword |= (1<<16);
 143         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 144
 145         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 146         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 147         value &= 0xbf;
 148         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 149
 150 }
 151
 152 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 153 {
 154         unsigned last_boot_normal_x = last_boot_normal();
 155
 156         /* Is this a cpu only reset? or Is this a secondary cpu? */
 157         if ((cpu_init_detectedx) || (!boot_cpu())) {
 158         if (last_boot_normal_x) {
 159         goto normal_image;
 160         } else {
 161         goto fallback_image;
 162         }
 163         }
 164
 165         /* Nothing special needs to be done to find bus 0 */
 166         /* Allow the HT devices to be found */
 167
 168         enumerate_ht_chain();
 169
 170         sio_setup();
 171
 172         /* Setup the ck804 */
 173         ck804_enable_rom();
 174
 175         /* Is this a deliberate reset by the bios */
 176 //      post_code(0x22);
 177         if (bios_reset_detected() && last_boot_normal_x) {
 178         goto normal_image;
 179         }
 180         /* This is the primary cpu how should I boot? */
 181         else if (do_normal_boot()) {
 182         goto normal_image;
 183         }
 184         else {
 185         goto fallback_image;
 186         }
 187  normal_image:
 188 //      post_code(0x23);
 189         __asm__ volatile ("jmp __normal_image"
 190         : /* outputs */
 191         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 192         );
 193
 194  fallback_image:
 195 //      post_code(0x25);
 196 #if CONFIG_HAVE_FAILOVER_BOOT==1
 197         __asm__ volatile ("jmp __fallback_image"
 198         : /* outputs */
 199         : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 200         )
 201 #endif
 202         ;
 203 }
 204 #endif
 205
 206 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 207
 208 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 209 {
 210 #if CONFIG_HAVE_FAILOVER_BOOT==1
 211         #if CONFIG_USE_FAILOVER_IMAGE==1
 212         failover_process(bist, cpu_init_detectedx);
 213         #else
 214         real_main(bist, cpu_init_detectedx);
 215         #endif
 216 #else
 217         #if CONFIG_USE_FALLBACK_IMAGE == 1
 218         failover_process(bist, cpu_init_detectedx);
 219         #endif
 220         real_main(bist, cpu_init_detectedx);
 221 #endif
 222 }
 223
 224 #if CONFIG_USE_FAILOVER_IMAGE==0
 225
 226 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 227 {
 228         static const uint16_t spd_addr [] = {
 229                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 230                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 231 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 232                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 233                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 234 #endif
 235         };
 236
 237         int needs_reset;
 238         unsigned bsp_apicid = 0;
 239
 240         struct mem_controller ctrl[8];
 241         unsigned nodes;
 242
 243         if (bist == 0) {
 244                 bsp_apicid = init_cpus(cpu_init_detectedx);
 245         }
 246
 247 //      post_code(0x32);
 248
 249         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 250         uart_init();
 251         console_init();
 252
 253         /* Halt if there was a built in self test failure */
 254         report_bist_failure(bist);
 255
 256         sio_gpio_setup();
 257
 258         setup_mb_resource_map();
 259
 260         needs_reset = setup_coherent_ht_domain();
 261
 262         wait_all_core0_started();
 263 #if CONFIG_LOGICAL_CPUS==1
 264         // It is said that we should start core1 after all core0 launched
 265         start_other_cores();
 266         wait_all_other_cores_started(bsp_apicid);
 267 #endif
 268
 269         needs_reset |= ht_setup_chains_x();
 270
 271         needs_reset |= ck804_early_setup_x();
 272
 273         if (needs_reset) {
 274                 printk_info("ht reset -\n");
 275                 soft_reset();
 276         }
 277
 278         allow_all_aps_stop(bsp_apicid);
 279
 280         nodes = get_nodes();
 281         //It's the time to set ctrl now;
 282         fill_mem_ctrl(nodes, ctrl, spd_addr);
 283
 284         enable_smbus();
 285
 286         memreset_setup();
 287         sdram_initialize(nodes, ctrl);
 288
 289         post_cache_as_ram();
 290 }
 291 #endif