2 * Tyan S2895 needs a different resource map
6 static void setup_mb_resource_map(void)
8 static const unsigned int register_values[] = {
9 /* Careful set limit registers before base registers which contain the enables */
10 /* DRAM Limit i Registers
19 * [ 2: 0] Destination Node ID
29 * [10: 8] Interleave select
30 * specifies the values of A[14:12] to use with interleave enable.
32 * [31:16] DRAM Limit Address i Bits 39-24
33 * This field defines the upper address bits of a 40 bit address
34 * that define the end of the DRAM region.
36 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
37 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
38 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
39 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
40 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
41 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
42 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
43 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
45 /* DRAM Base i Registers
57 * [ 1: 1] Write Enable
61 * [10: 8] Interleave Enable
63 * 001 = Interleave on A[12] (2 nodes)
65 * 011 = Interleave on A[12] and A[14] (4 nodes)
69 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
71 * [13:16] DRAM Base Address i Bits 39-24
72 * This field defines the upper address bits of a 40-bit address
73 * that define the start of the DRAM region.
75 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
76 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
77 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
78 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
79 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
80 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
81 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
82 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
84 /* Memory-Mapped I/O Limit i Registers
93 * [ 2: 0] Destination Node ID
103 * [ 5: 4] Destination Link ID
110 * 0 = CPU writes may be posted
111 * 1 = CPU writes must be non-posted
112 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
113 * This field defines the upp adddress bits of a 40-bit address that
114 * defines the end of a memory-mapped I/O region n
116 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
117 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
118 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
119 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
120 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
121 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
122 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
123 // PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
125 /* Memory-Mapped I/O Base i Registers
134 * [ 0: 0] Read Enable
137 * [ 1: 1] Write Enable
138 * 0 = Writes disabled
140 * [ 2: 2] Cpu Disable
141 * 0 = Cpu can use this I/O range
142 * 1 = Cpu requests do not use this I/O range
144 * 0 = base/limit registers i are read/write
145 * 1 = base/limit registers i are read-only
147 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
148 * This field defines the upper address bits of a 40bit address
149 * that defines the start of memory-mapped I/O region i
151 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
152 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
153 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
154 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
155 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
156 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
157 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
158 // PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
160 /* PCI I/O Limit i Registers
165 * [ 2: 0] Destination Node ID
175 * [ 5: 4] Destination Link ID
181 * [24:12] PCI I/O Limit Address i
182 * This field defines the end of PCI I/O region n
185 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
186 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x01fff001, // need to talk to ANALOG of second CK804 to release PCI E reset
187 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
188 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
190 /* PCI I/O Base i Registers
195 * [ 0: 0] Read Enable
198 * [ 1: 1] Write Enable
199 * 0 = Writes Disabled
203 * 0 = VGA matches Disabled
204 * 1 = matches all address < 64K and where A[9:0] is in the
205 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
207 * 0 = ISA matches Disabled
208 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
209 * from matching agains this base/limit pair
211 * [24:12] PCI I/O Base i
212 * This field defines the start of PCI I/O region n
215 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
216 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00008033,
217 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
218 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
220 /* Config Base and Limit i Registers
225 * [ 0: 0] Read Enable
228 * [ 1: 1] Write Enable
229 * 0 = Writes Disabled
231 * [ 2: 2] Device Number Compare Enable
232 * 0 = The ranges are based on bus number
233 * 1 = The ranges are ranges of devices on bus 0
235 * [ 6: 4] Destination Node
245 * [ 9: 8] Destination Link
251 * [23:16] Bus Number Base i
252 * This field defines the lowest bus number in configuration region i
253 * [31:24] Bus Number Limit i
254 * This field defines the highest bus number in configuration region i
256 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x07000003, /* link 0 of cpu 0 --> Nvidia CK 804 Pro */
257 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x7f080203, /* link 2 of cpu 0 --> AMD8131 */
258 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0xff800013, /* link 0 of cpu 1 --> Nvidia CK 804 Slave */
259 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, /*113 link 1 of cpu 1 --> HT connector */
264 max = ARRAY_SIZE(register_values);
265 setup_resource_map(register_values, max);