1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/amd/amdk8_sysconf.h>
8 extern unsigned char bus_ck804_0; //1
9 extern unsigned char bus_ck804_1; //2
10 extern unsigned char bus_ck804_2; //3
11 extern unsigned char bus_ck804_3; //4
12 extern unsigned char bus_ck804_4; //5
13 extern unsigned char bus_ck804_5; //6
14 extern unsigned char bus_8131_0; //7
15 extern unsigned char bus_8131_1; //8
16 extern unsigned char bus_8131_2; //9
17 extern unsigned char bus_ck804b_0;//a
18 extern unsigned char bus_ck804b_1;//b
19 extern unsigned char bus_ck804b_2;//c
20 extern unsigned char bus_ck804b_3;//d
21 extern unsigned char bus_ck804b_4;//e
22 extern unsigned char bus_ck804b_5;//f
23 extern unsigned apicid_ck804;
24 extern unsigned apicid_8131_1;
25 extern unsigned apicid_8131_2;
26 extern unsigned apicid_ck804b;
28 extern unsigned sbdn3;
29 extern unsigned sbdnb;
31 static void *smp_write_config_table(void *v)
33 struct mp_config_table *mc;
37 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
39 mptable_init(mc, LOCAL_APIC_ADDR);
41 smp_write_processors(mc);
46 mptable_write_buses(mc, NULL, &bus_isa);
48 /*I/O APICs: APIC ID Version State Address*/
54 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
56 res = find_resource(dev, PCI_BASE_ADDRESS_1);
58 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
61 /* Initialize interrupt mapping*/
64 pci_write_config32(dev, 0x7c, dword);
67 pci_write_config32(dev, 0x80, dword);
70 pci_write_config32(dev, 0x84, dword);
74 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
76 res = find_resource(dev, PCI_BASE_ADDRESS_0);
78 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
81 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
83 res = find_resource(dev, PCI_BASE_ADDRESS_0);
85 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
89 if(sysconf.pci1234[2] & 0xf) {
90 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
92 res = find_resource(dev, PCI_BASE_ADDRESS_1);
94 smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
97 dword = 0x0000d218; // Why does the factory BIOS have 0?
98 pci_write_config32(dev, 0x7c, dword);
101 pci_write_config32(dev, 0x80, dword);
103 dword = 0x00000d00; // Same here.
104 pci_write_config32(dev, 0x84, dword);
111 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
113 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
114 // Onboard ck804 smbus
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
118 // Onboard ck804 USB 1.1
119 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
121 // Onboard ck804 USB 2
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
124 // Onboard ck804 Audio
125 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
127 // Onboard ck804 SATA 0
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
130 // Onboard ck804 SATA 1
131 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
134 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
142 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
146 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16
149 if(sysconf.pci1234[2] & 0xf) {
151 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
155 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
161 //Slot 4 PCI-X 100/66
163 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
168 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
173 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
178 //Slot 6 PCIX 133/100/66
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
183 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
184 mptable_lintsrc(mc, bus_isa);
185 /* There is no extension information... */
187 /* Compute the checksums */
188 return mptable_finalize(mc);
191 unsigned long write_smp_table(unsigned long addr)
194 v = smp_write_floating_table(addr, 0);
195 return (unsigned long)smp_write_config_table(v);