src/mainboard/tyan/s2895/mptable.c

   1 #include <console/console.h>
   2 #include <arch/smp/mpspec.h>
   3 #include <device/pci.h>
   4 #include <string.h>
   5 #include <stdint.h>
   6
   7 #if CONFIG_LOGICAL_CPUS==1
   8 #include <cpu/amd/dualcore.h>
   9 #endif
  10
  11 void *smp_write_config_table(void *v)
  12 {
  13         static const char sig[4] = "PCMP";
  14         static const char oem[8] = "TYAN    ";
  15         static const char productid[12] = "S2895       ";
  16         struct mp_config_table *mc;
  17
  18         unsigned char bus_num;
  19         unsigned char bus_isa;
  20         unsigned char bus_ck804_0; //1
  21         unsigned char bus_ck804_1; //2
  22         unsigned char bus_ck804_2; //3
  23         unsigned char bus_ck804_3; //4
  24         unsigned char bus_ck804_4; //5
  25         unsigned char bus_ck804_5; //6
  26         unsigned char bus_8131_0;  //7
  27         unsigned char bus_8131_1;  //8
  28         unsigned char bus_8131_2;  //9
  29         unsigned char bus_ck804b_0;//a
  30         unsigned char bus_ck804b_1;//b
  31         unsigned char bus_ck804b_2;//c
  32         unsigned char bus_ck804b_3;//d
  33         unsigned char bus_ck804b_4;//e
  34         unsigned char bus_ck804b_5;//f
  35         unsigned apicid_base;
  36         unsigned apicid_ck804;
  37         unsigned apicid_8131_1;
  38         unsigned apicid_8131_2;
  39         unsigned apicid_ck804b;
  40
  41
  42         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
  43         memset(mc, 0, sizeof(*mc));
  44
  45         memcpy(mc->mpc_signature, sig, sizeof(sig));
  46         mc->mpc_length = sizeof(*mc); /* initially just the header */
  47         mc->mpc_spec = 0x04;
  48         mc->mpc_checksum = 0; /* not yet computed */
  49         memcpy(mc->mpc_oem, oem, sizeof(oem));
  50         memcpy(mc->mpc_productid, productid, sizeof(productid));
  51         mc->mpc_oemptr = 0;
  52         mc->mpc_oemsize = 0;
  53         mc->mpc_entry_count = 0; /* No entries yet... */
  54         mc->mpc_lapic = LAPIC_ADDR;
  55         mc->mpe_length = 0;
  56         mc->mpe_checksum = 0;
  57         mc->reserved = 0;
  58
  59         smp_write_processors(mc);
  60
  61        {
  62                 device_t dev;
  63
  64
  65                 /* CK804 */
  66                 bus_ck804_0 = 1;
  67                 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x09,0));
  68                 if (dev) {
  69                         bus_ck804_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  70                         bus_ck804_5 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  71                         bus_ck804_5++;
  72                 }
  73                 else {
  74                         printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n", CK804_DEVN_BASE + 0x09);
  75
  76                         bus_ck804_1 = 2;
  77                         bus_ck804_5 = 3;
  78
  79                 }
  80
  81                 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
  82                 if (dev) {
  83                         bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  84                         bus_8131_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  85                         bus_8131_0++;
  86                 }
  87                 else {
  88                         printk_debug("ERROR - could not find PCI 1:%02x.0, using defaults\n",CK804_DEVN_BASE + 0x0e);
  89
  90                         bus_8131_0 = bus_ck804_5+1;
  91                 }
  92
  93                 /* 8131-1 */
  94                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x01,0));
  95                 if (dev) {
  96                         bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
  97                         bus_8131_2 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
  98                         bus_8131_2++;
  99                 }
 100                 else {
 101                         printk_debug("ERROR - could not find PCI %02x:01.0, using defaults\n", bus_8131_0);
 102
 103                         bus_8131_1 = bus_8131_0+1;
 104                         bus_8131_2 = bus_8131_0+2;
 105                 }
 106                 /* 8131-2 */
 107                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x02,0));
 108                 if (dev) {
 109                         bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 110                         bus_ck804b_0 = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 111                         bus_ck804b_0++;
 112                 }
 113                 else {
 114                         printk_debug("ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
 115
 116                         bus_8131_2 = bus_8131_1+1;
 117                         bus_ck804b_0 = bus_8131_1+2;
 118                 }
 119
 120                 /* CK804b */
 121
 122                 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x0e,0));
 123                 if (dev) {
 124                         bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
 125                         bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
 126                         bus_isa++;
 127                 }
 128                 else {
 129                         printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,CK804_DEVN_BASE+0x0e);
 130 #if 1
 131                         bus_ck804b_5 = bus_ck804b_0+1;
 132 #endif
 133
 134                         bus_isa = bus_ck804b_5+1;
 135                 }
 136
 137         }
 138
 139
 140
 141 /*Bus:          Bus ID  Type*/
 142        /* define bus and isa numbers */
 143         for(bus_num = 0; bus_num < bus_isa; bus_num++) {
 144                 smp_write_bus(mc, bus_num, "PCI   ");
 145         }
 146         smp_write_bus(mc, bus_isa, "ISA   ");
 147
 148 /*I/O APICs:    APIC ID Version State           Address*/
 149 #if CONFIG_LOGICAL_CPUS==1
 150         apicid_base = get_apicid_base(4);
 151 #else
 152         apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
 153 #endif
 154         apicid_ck804 = apicid_base;
 155         apicid_8131_1 = apicid_base+1;
 156         apicid_8131_2 = apicid_base+2;
 157         apicid_ck804b = apicid_base+3;
 158 //      smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
 159         {
 160                 device_t dev;
 161                 struct resource *res;
 162                 uint32_t dword;
 163
 164                 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(CK804_DEVN_BASE+ 0x1,0));
 165                 if (dev) {
 166                         res = find_resource(dev, PCI_BASE_ADDRESS_1);
 167                         if (res) {
 168                                 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
 169                         }
 170
 171                         dword = 0x0120d218;
 172                         pci_write_config32(dev, 0x7c, dword);
 173
 174                         dword = 0x12008a00;
 175                         pci_write_config32(dev, 0x80, dword);
 176
 177                         dword = 0x00080d7d;
 178                         pci_write_config32(dev, 0x84, dword);
 179
 180                 }
 181
 182                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x1,1));
 183                 if (dev) {
 184                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 185                         if (res) {
 186                                 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
 187                         }
 188                 }
 189                 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(0x2,1));
 190                 if (dev) {
 191                         res = find_resource(dev, PCI_BASE_ADDRESS_0);
 192                         if (res) {
 193                                 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
 194                         }
 195                 }
 196
 197                 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(CK804_DEVN_BASE + 0x1,0));
 198                 if (dev) {
 199                         res = find_resource(dev, PCI_BASE_ADDRESS_1);
 200                         if (res) {
 201                                 smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
 202                         }
 203
 204                         dword = 0x0000d218;
 205                         pci_write_config32(dev, 0x7c, dword);
 206
 207                         dword = 0x00000000;
 208                         pci_write_config32(dev, 0x80, dword);
 209
 210                         dword = 0x00000d00;
 211                         pci_write_config32(dev, 0x84, dword);
 212
 213                 }
 214
 215         }
 216
 217 /*I/O Ints:     Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#
 218 */      smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_ck804, 0x0);
 219         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x1, apicid_ck804, 0x1);
 220         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x0, apicid_ck804, 0x2);
 221         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x3, apicid_ck804, 0x3);
 222         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x4, apicid_ck804, 0x4);
 223         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x6, apicid_ck804, 0x6);
 224         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x7, apicid_ck804, 0x7);
 225         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0x8, apicid_ck804, 0x8);
 226         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xc, apicid_ck804, 0xc);
 227         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xd, apicid_ck804, 0xd);
 228         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xe, apicid_ck804, 0xe);
 229         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH,  bus_isa, 0xf, apicid_ck804, 0xf);
 230
 231         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa);
 232
 233         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15);
 234
 235         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14);
 236
 237         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+4)<<2)|0, apicid_ck804, 0x14);
 238
 239         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17);
 240
 241         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16);
 242
 243         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +0x0a)<<2)|0, apicid_ck804, 0x15);
 244
 245 #if 1
 246         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); //
 247         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|1, apicid_ck804, 0x13); //
 248         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|2, apicid_ck804, 0x10); //
 249         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|3, apicid_ck804, 0x11); //
 250 #endif
 251
 252         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); //
 253
 254         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|0, apicid_ck804, 0x10); //
 255         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|1, apicid_ck804, 0x11); //
 256         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|2, apicid_ck804, 0x12); //
 257         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|3, apicid_ck804, 0x13); //
 258
 259         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((CK804_DEVN_BASE+0x0a)<<2)|0, apicid_ck804b, 0x15);//
 260
 261 #if 1
 262         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|0, apicid_ck804b, 0x12);//
 263         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|1, apicid_ck804b, 0x13); //
 264         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|2, apicid_ck804b, 0x10); //
 265         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|3, apicid_ck804b, 0x11); //
 266 #endif
 267
 268
 269         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|0, apicid_8131_2, 0x0); //
 270         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|1, apicid_8131_2, 0x1);
 271         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|2, apicid_8131_2, 0x2); //
 272         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|3, apicid_8131_2, 0x3); //
 273
 274         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|0, apicid_8131_2, 0x1); //
 275         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|1, apicid_8131_2, 0x2);
 276         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|2, apicid_8131_2, 0x3);//
 277         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|3, apicid_8131_2, 0x0);//
 278
 279
 280         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, apicid_8131_2, 0x2); //
 281         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, apicid_8131_2, 0x3);
 282
 283         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|0, apicid_8131_1, 0x0); //
 284         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|1, apicid_8131_1, 0x1);//
 285         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|2, apicid_8131_1, 0x2);//
 286         smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|3, apicid_8131_1, 0x3);//
 287
 288 /*Local Ints:   Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN#*/
 289         smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
 290         smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
 291         /* There is no extension information... */
 292
 293         /* Compute the checksums */
 294         mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
 295         mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
 296         printk_debug("Wrote the mp table end at: %p - %p\n",
 297                 mc, smp_next_mpe_entry(mc));
 298         return smp_next_mpe_entry(mc);
 299 }
 300
 301 unsigned long write_smp_table(unsigned long addr)
 302 {
 303         void *v;
 304         v = smp_write_floating_table(addr);
 305         return (unsigned long)smp_write_config_table(v);
 306 }