1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/amd/amdk8_sysconf.h>
8 extern unsigned char bus_isa;
9 extern unsigned char bus_ck804_0; //1
10 extern unsigned char bus_ck804_1; //2
11 extern unsigned char bus_ck804_2; //3
12 extern unsigned char bus_ck804_3; //4
13 extern unsigned char bus_ck804_4; //5
14 extern unsigned char bus_ck804_5; //6
15 extern unsigned char bus_8131_0; //7
16 extern unsigned char bus_8131_1; //8
17 extern unsigned char bus_8131_2; //9
18 extern unsigned char bus_ck804b_0;//a
19 extern unsigned char bus_ck804b_1;//b
20 extern unsigned char bus_ck804b_2;//c
21 extern unsigned char bus_ck804b_3;//d
22 extern unsigned char bus_ck804b_4;//e
23 extern unsigned char bus_ck804b_5;//f
24 extern unsigned apicid_ck804;
25 extern unsigned apicid_8131_1;
26 extern unsigned apicid_8131_2;
27 extern unsigned apicid_ck804b;
29 extern unsigned sbdn3;
30 extern unsigned sbdnb;
32 static void *smp_write_config_table(void *v)
34 struct mp_config_table *mc;
36 unsigned char bus_num;
39 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
41 mptable_init(mc, "S2895 ", LAPIC_ADDR);
43 smp_write_processors(mc);
49 /* define bus and isa numbers */
50 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
51 smp_write_bus(mc, bus_num, "PCI ");
53 smp_write_bus(mc, bus_isa, "ISA ");
55 /*I/O APICs: APIC ID Version State Address*/
61 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
63 res = find_resource(dev, PCI_BASE_ADDRESS_1);
65 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
68 /* Initialize interrupt mapping*/
71 pci_write_config32(dev, 0x7c, dword);
74 pci_write_config32(dev, 0x80, dword);
77 pci_write_config32(dev, 0x84, dword);
81 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
83 res = find_resource(dev, PCI_BASE_ADDRESS_0);
85 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
88 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
90 res = find_resource(dev, PCI_BASE_ADDRESS_0);
92 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
96 if(sysconf.pci1234[2] & 0xf) {
97 dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x1,0));
99 res = find_resource(dev, PCI_BASE_ADDRESS_1);
101 smp_write_ioapic(mc, apicid_ck804b, 0x11, res->base);
104 dword = 0x0000d218; // Why does the factory BIOS have 0?
105 pci_write_config32(dev, 0x7c, dword);
108 pci_write_config32(dev, 0x80, dword);
110 dword = 0x00000d00; // Same here.
111 pci_write_config32(dev, 0x84, dword);
118 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
120 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
121 // Onboard ck804 smbus
122 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa);
125 // Onboard ck804 USB 1.1
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
128 // Onboard ck804 USB 2
129 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
131 // Onboard ck804 Audio
132 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+4)<<2)|0, apicid_ck804, 0x14); // 20
134 // Onboard ck804 SATA 0
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
137 // Onboard ck804 SATA 1
138 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
141 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +0x0a)<<2)|0, apicid_ck804, 0x15); // 21
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
149 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x05<<2)|0, apicid_ck804, 0x13); // 19
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16
156 if(sysconf.pci1234[2] & 0xf) {
158 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_0, ((sbdnb+0x0a)<<2)|0, apicid_ck804b, 0x15);//24+4+4+21=53
162 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804b_5, (0x00<<2)|i, apicid_ck804b, 0x10 + (2+i+4-sbdnb%4)%4);
168 //Slot 4 PCI-X 100/66
170 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (4<<2)|i, apicid_8131_2, (0+i)%4);
175 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (1+i)%4); // 29
180 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|i, apicid_8131_2, (2+i)%4); //30
185 //Slot 6 PCIX 133/100/66
187 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (4<<2)|i, apicid_8131_1, (0+i)%4); //24
190 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
191 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
192 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
193 /* There is no extension information... */
195 /* Compute the checksums */
196 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
197 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
198 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
199 mc, smp_next_mpe_entry(mc));
200 return smp_next_mpe_entry(mc);
203 unsigned long write_smp_table(unsigned long addr)
206 v = smp_write_floating_table(addr);
207 return (unsigned long)smp_write_config_table(v);