6 #include <device/pci_def.h>
8 #include <device/pnp_def.h>
9 #include <arch/romcc_io.h>
10 #include <cpu/x86/lapic.h>
11 #include "option_table.h"
12 #include "pc80/mc146818rtc_early.c"
14 #include "cpu/x86/lapic/boot_cpu.c"
15 #include "northbridge/amd/amdk8/reset_test.c"
17 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
18 #include "northbridge/amd/amdk8/early_ht.c"
20 #define post_code(x) outb(x, 0x80)
22 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
23 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
24 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
25 #define SUPERIO_GPIO_IO_BASE 0x400
27 static void sio_setup(void)
34 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
36 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
38 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
40 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
41 dword |= (1<<29)|(1<<0);
42 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
44 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
46 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
48 lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
49 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
51 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
55 void mainboard_bsp_init()
57 /* Nothing special needs to be done to find bus 0 */
58 /* Allow the HT devices to be found */
68 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
70 unsigned last_boot_normal_x = last_boot_normal();
72 /* Is this a cpu only reset? or Is this a secondary cpu? */
73 if ((cpu_init_detectedx) || (!boot_cpu())) {
74 if (last_boot_normal_x) {
83 /* Is this a deliberate reset by the bios */
85 if (bios_reset_detected() && last_boot_normal_x) {
88 /* This is the primary cpu how should I boot? */
89 else if (do_normal_boot()) {
97 __asm__ volatile ("jmp __normal_image"
99 : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
104 __asm__ volatile ("jmp __fallback_image"
106 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */