src/mainboard/tyan/s2895/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4
   5 #define K8_ALLOCATE_IO_RANGE 1
   6 //#define K8_SCAN_PCI_BUS 1
   7
   8
   9 #define K8_4RANK_DIMM_SUPPORT 1
  10
  11 #if CONFIG_LOGICAL_CPUS==1
  12 #define SET_NB_CFG_54 1
  13 #endif
  14
  15
  16 #include <stdint.h>
  17 #include <device/pci_def.h>
  18 #include <arch/io.h>
  19 #include <device/pnp_def.h>
  20 #include <arch/romcc_io.h>
  21 #include <cpu/x86/lapic.h>
  22 #include "option_table.h"
  23 #include "pc80/mc146818rtc_early.c"
  24 #include "pc80/serial.c"
  25 #include "arch/i386/lib/console.c"
  26 #include "ram/ramtest.c"
  27
  28 #include <cpu/amd/model_fxx_rev.h>
  29 #include "northbridge/amd/amdk8/incoherent_ht.c"
  30 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  31 #include "northbridge/amd/amdk8/raminit.h"
  32 #include "cpu/amd/model_fxx/apic_timer.c"
  33 #include "lib/delay.c"
  34
  35 #if CONFIG_USE_INIT == 0
  36 #include "lib/memcpy.c"
  37 #endif
  38
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include "northbridge/amd/amdk8/debug.c"
  42 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  43
  44 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  45 #include "cpu/x86/bist.h"
  46
  47 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  48
  49 #include "northbridge/amd/amdk8/setup_resource_map.c"
  50
  51 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  52
  53 static void hard_reset(void)
  54 {
  55         set_bios_reset();
  56
  57         /* full reset */
  58         outb(0x0a, 0x0cf9);
  59         outb(0x0e, 0x0cf9);
  60 }
  61
  62 static void soft_reset(void)
  63 {
  64         set_bios_reset();
  65 #if 1
  66         /* link reset */
  67         outb(0x02, 0x0cf9);
  68         outb(0x06, 0x0cf9);
  69 #endif
  70 }
  71
  72 static void memreset_setup(void)
  73 {
  74 }
  75
  76 static void memreset(int controllers, const struct mem_controller *ctrl)
  77 {
  78 }
  79
  80 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  81
  82 #define SUPERIO_GPIO_IO_BASE 0x400
  83
  84 static void sio_gpio_setup(void){
  85
  86         unsigned value;
  87
  88         /*Enable onboard scsi*/
  89         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  90         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  91         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  92
  93 }
  94
  95 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  96 {
  97         /* nothing to do */
  98 }
  99
 100 static inline int spd_read_byte(unsigned device, unsigned address)
 101 {
 102         return smbus_read_byte(device, address);
 103 }
 104
 105
 106 #include "northbridge/amd/amdk8/raminit.c"
 107 #include "northbridge/amd/amdk8/coherent_ht.c"
 108 #include "sdram/generic_sdram.c"
 109
 110  /* tyan does not want the default */
 111 #include "resourcemap.c"
 112
 113 #include "cpu/amd/dualcore/dualcore.c"
 114
 115 #define CK804_NUM 2
 116 #define CK804B_BUSN 0x80
 117 #define CK804_USE_NIC 1
 118 #define CK804_USE_ACI 1
 119
 120 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 121
 122 //set GPIO to input mode
 123 #define CK804_MB_SETUP \
 124                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 125                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 126                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 127                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 128                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 129                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 130
 131 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 132
 133 #include "cpu/amd/car/copy_and_run.c"
 134
 135 #include "cpu/amd/car/post_cache_as_ram.c"
 136
 137 #include "cpu/amd/model_fxx/init_cpus.c"
 138
 139
 140 #if USE_FALLBACK_IMAGE == 1
 141
 142 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 143 #include "northbridge/amd/amdk8/early_ht.c"
 144
 145
 146 static void sio_setup(void)
 147 {
 148
 149         unsigned value;
 150         uint32_t dword;
 151         uint8_t byte;
 152
 153
 154         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 155
 156         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 157         byte |= 0x20;
 158         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 159
 160         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 161         dword |= (1<<29)|(1<<0);
 162         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 163
 164 #if  1
 165         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 166
 167         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 168         value &= 0xbf;
 169         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 170 #endif
 171
 172 }
 173
 174 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 175 {
 176         unsigned last_boot_normal_x = last_boot_normal();
 177
 178         /* Is this a cpu only reset? or Is this a secondary cpu? */
 179         if ((cpu_init_detectedx) || (!boot_cpu())) {
 180                 if (last_boot_normal_x) {
 181                         goto normal_image;
 182                 } else {
 183                         goto fallback_image;
 184                 }
 185         }
 186
 187         /* Nothing special needs to be done to find bus 0 */
 188         /* Allow the HT devices to be found */
 189
 190         enumerate_ht_chain();
 191
 192         sio_setup();
 193
 194         /* Setup the ck804 */
 195         ck804_enable_rom();
 196
 197         /* Is this a deliberate reset by the bios */
 198         if (bios_reset_detected() && last_boot_normal_x) {
 199                 goto normal_image;
 200         }
 201         /* This is the primary cpu how should I boot? */
 202         else if (do_normal_boot()) {
 203                 goto normal_image;
 204         }
 205         else {
 206                 goto fallback_image;
 207         }
 208  normal_image:
 209         __asm__ volatile ("jmp __normal_image"
 210                 : /* outputs */
 211                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 212                 );
 213
 214  fallback_image:
 215         ;
 216 }
 217 #endif
 218
 219 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 220
 221 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 222 {
 223
 224 #if USE_FALLBACK_IMAGE == 1
 225         failover_process(bist, cpu_init_detectedx);
 226 #endif
 227         real_main(bist, cpu_init_detectedx);
 228
 229 }
 230
 231 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 232 {
 233         static const uint16_t spd_addr [] = {
 234                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 235                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 236 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 237                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 238                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 239 #endif
 240         };
 241
 242         int needs_reset;
 243         unsigned cpu_reset = 0;
 244         unsigned bsp_apicid = 0;
 245
 246         struct mem_controller ctrl[8];
 247         unsigned nodes;
 248
 249         if (bist == 0) {
 250                 bsp_apicid = init_cpus(cpu_init_detectedx);
 251         }
 252
 253         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 254         uart_init();
 255         console_init();
 256
 257         /* Halt if there was a built in self test failure */
 258         report_bist_failure(bist);
 259
 260         setup_s2895_resource_map();
 261
 262         needs_reset = setup_coherent_ht_domain();
 263
 264 #if CONFIG_LOGICAL_CPUS==1
 265         // It is said that we should start core1 after all core0 launched
 266         wait_all_core0_started();
 267         start_other_cores();
 268 #endif
 269
 270         wait_all_aps_started(bsp_apicid);
 271
 272         needs_reset |= ht_setup_chains_x();
 273
 274         needs_reset |= ck804_early_setup_x();
 275
 276         if (needs_reset) {
 277                 print_info("ht reset -\r\n");
 278                 soft_reset();
 279         }
 280
 281         allow_all_aps_stop(bsp_apicid);
 282
 283         nodes = get_nodes();
 284         //It's the time to set ctrl now;
 285         fill_mem_ctrl(nodes, ctrl, spd_addr);
 286
 287         enable_smbus();
 288
 289         memreset_setup();
 290         sdram_initialize(nodes, ctrl);
 291
 292         post_cache_as_ram(cpu_reset);
 293 }