src/mainboard/tyan/s2895/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define K8_ALLOCATE_IO_RANGE 1
   5 //#define K8_SCAN_PCI_BUS 1
   6
   7 //used by raminit
   8 #define QRANK_DIMM_SUPPORT 1
   9
  10 #if CONFIG_LOGICAL_CPUS==1
  11 #define SET_NB_CFG_54 1
  12 #endif
  13
  14 #include <stdint.h>
  15 #include <string.h>
  16 #include <device/pci_def.h>
  17 #include <arch/io.h>
  18 #include <device/pnp_def.h>
  19 #include <arch/romcc_io.h>
  20 #include <cpu/x86/lapic.h>
  21 #include "option_table.h"
  22 #include "pc80/mc146818rtc_early.c"
  23
  24 #if CONFIG_USE_FAILOVER_IMAGE==0
  25 #include "pc80/serial.c"
  26 #include "arch/i386/lib/console.c"
  27 #include "lib/ramtest.c"
  28
  29 #include <cpu/amd/model_fxx_rev.h>
  30
  31 #include "northbridge/amd/amdk8/incoherent_ht.c"
  32 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  33 #include "northbridge/amd/amdk8/raminit.h"
  34 #include "cpu/amd/model_fxx/apic_timer.c"
  35 #include "lib/delay.c"
  36
  37 #endif
  38
  39 #include "cpu/x86/lapic/boot_cpu.c"
  40 #include "northbridge/amd/amdk8/reset_test.c"
  41 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  42 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  43 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  44
  45 #define SUPERIO_GPIO_IO_BASE 0x400
  46
  47 #if CONFIG_USE_FAILOVER_IMAGE==0
  48
  49 #include "cpu/x86/bist.h"
  50
  51 #include "northbridge/amd/amdk8/debug.c"
  52
  53 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  54
  55 #include "northbridge/amd/amdk8/setup_resource_map.c"
  56
  57 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  58
  59 static void memreset_setup(void)
  60 {
  61 }
  62
  63 static void memreset(int controllers, const struct mem_controller *ctrl)
  64 {
  65 }
  66
  67 static void sio_gpio_setup(void){
  68
  69         unsigned value;
  70
  71         /*Enable onboard scsi*/
  72         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  73         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  74         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  75
  76 }
  77
  78 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  79 {
  80         /* nothing to do */
  81 }
  82
  83 static inline int spd_read_byte(unsigned device, unsigned address)
  84 {
  85         return smbus_read_byte(device, address);
  86 }
  87
  88 #include "northbridge/amd/amdk8/raminit.c"
  89 #include "northbridge/amd/amdk8/coherent_ht.c"
  90 #include "lib/generic_sdram.c"
  91
  92  /* tyan does not want the default */
  93 #include "resourcemap.c"
  94
  95 #include "cpu/amd/dualcore/dualcore.c"
  96
  97 #define CK804_NUM 2
  98 #define CK804_USE_NIC 1
  99 #define CK804_USE_ACI 1
 100
 101 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 102
 103 //set GPIO to input mode
 104 #define CK804_MB_SETUP \
 105         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 106         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 107         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 108         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 109         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 110         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 111
 112 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 113
 114 #include "cpu/amd/car/copy_and_run.c"
 115
 116 #include "cpu/amd/car/post_cache_as_ram.c"
 117
 118 #include "cpu/amd/model_fxx/init_cpus.c"
 119
 120 #endif
 121
 122 #if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 123
 124 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 125 #include "northbridge/amd/amdk8/early_ht.c"
 126
 127 static void sio_setup(void)
 128 {
 129
 130         unsigned value;
 131         uint32_t dword;
 132         uint8_t byte;
 133
 134         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 135
 136         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 137         byte |= 0x20;
 138         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 139
 140         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 141         dword |= (1<<29)|(1<<0);
 142         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 143
 144         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 145         dword |= (1<<16);
 146         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 147
 148         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 149         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 150         value &= 0xbf;
 151         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 152
 153 }
 154
 155 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 156 {
 157         unsigned last_boot_normal_x = last_boot_normal();
 158
 159         /* Is this a cpu only reset? or Is this a secondary cpu? */
 160         if ((cpu_init_detectedx) || (!boot_cpu())) {
 161         if (last_boot_normal_x) {
 162         goto normal_image;
 163         } else {
 164         goto fallback_image;
 165         }
 166         }
 167
 168         /* Nothing special needs to be done to find bus 0 */
 169         /* Allow the HT devices to be found */
 170
 171         enumerate_ht_chain();
 172
 173         sio_setup();
 174
 175         /* Setup the ck804 */
 176         ck804_enable_rom();
 177
 178         /* Is this a deliberate reset by the bios */
 179 //      post_code(0x22);
 180         if (bios_reset_detected() && last_boot_normal_x) {
 181         goto normal_image;
 182         }
 183         /* This is the primary cpu how should I boot? */
 184         else if (do_normal_boot()) {
 185         goto normal_image;
 186         }
 187         else {
 188         goto fallback_image;
 189         }
 190  normal_image:
 191 //      post_code(0x23);
 192         __asm__ volatile ("jmp __normal_image"
 193         : /* outputs */
 194         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 195         );
 196
 197  fallback_image:
 198 //      post_code(0x25);
 199 #if CONFIG_HAVE_FAILOVER_BOOT==1
 200         __asm__ volatile ("jmp __fallback_image"
 201         : /* outputs */
 202         : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 203         )
 204 #endif
 205         ;
 206 }
 207 #endif
 208
 209 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 210
 211 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 212 {
 213 #if CONFIG_HAVE_FAILOVER_BOOT==1
 214         #if CONFIG_USE_FAILOVER_IMAGE==1
 215         failover_process(bist, cpu_init_detectedx);
 216         #else
 217         real_main(bist, cpu_init_detectedx);
 218         #endif
 219 #else
 220         #if CONFIG_USE_FALLBACK_IMAGE == 1
 221         failover_process(bist, cpu_init_detectedx);
 222         #endif
 223         real_main(bist, cpu_init_detectedx);
 224 #endif
 225 }
 226
 227 #if CONFIG_USE_FAILOVER_IMAGE==0
 228
 229 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 230 {
 231         static const uint16_t spd_addr [] = {
 232                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 233                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 234 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 235                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 236                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 237 #endif
 238         };
 239
 240         int needs_reset;
 241         unsigned bsp_apicid = 0;
 242
 243         struct mem_controller ctrl[8];
 244         unsigned nodes;
 245
 246         if (bist == 0) {
 247                 bsp_apicid = init_cpus(cpu_init_detectedx);
 248         }
 249
 250 //      post_code(0x32);
 251
 252         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 253         uart_init();
 254         console_init();
 255
 256         /* Halt if there was a built in self test failure */
 257         report_bist_failure(bist);
 258
 259         sio_gpio_setup();
 260
 261         setup_mb_resource_map();
 262 #if 0
 263         dump_pci_device(PCI_DEV(0, 0x18, 0));
 264         dump_pci_device(PCI_DEV(0, 0x19, 0));
 265 #endif
 266
 267         needs_reset = setup_coherent_ht_domain();
 268
 269         wait_all_core0_started();
 270 #if CONFIG_LOGICAL_CPUS==1
 271         // It is said that we should start core1 after all core0 launched
 272         start_other_cores();
 273         wait_all_other_cores_started(bsp_apicid);
 274 #endif
 275
 276         needs_reset |= ht_setup_chains_x();
 277
 278         needs_reset |= ck804_early_setup_x();
 279
 280         if (needs_reset) {
 281                 printk_info("ht reset -\r\n");
 282                 soft_reset();
 283         }
 284
 285         allow_all_aps_stop(bsp_apicid);
 286
 287         nodes = get_nodes();
 288         //It's the time to set ctrl now;
 289         fill_mem_ctrl(nodes, ctrl, spd_addr);
 290
 291         enable_smbus();
 292
 293         memreset_setup();
 294         sdram_initialize(nodes, ctrl);
 295
 296         post_cache_as_ram();
 297 }
 298 #endif