5 #define K8_ALLOCATE_IO_RANGE 1
6 //#define K8_SCAN_PCI_BUS 1
9 #define QRANK_DIMM_SUPPORT 1
11 #if CONFIG_LOGICAL_CPUS==1
12 #define SET_NB_CFG_54 1
17 #include <device/pci_def.h>
19 #include <device/pnp_def.h>
20 #include <arch/romcc_io.h>
21 #include <cpu/x86/lapic.h>
22 #include "option_table.h"
23 #include "pc80/mc146818rtc_early.c"
25 #if USE_FAILOVER_IMAGE==0
26 #include "pc80/serial.c"
27 #include "arch/i386/lib/console.c"
28 #include "ram/ramtest.c"
31 static void post_code(uint8_t value) {
34 for(i=0;i<0x8000;i++) {
41 #include <cpu/amd/model_fxx_rev.h>
43 #include "northbridge/amd/amdk8/incoherent_ht.c"
44 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
45 #include "northbridge/amd/amdk8/raminit.h"
46 #include "cpu/amd/model_fxx/apic_timer.c"
47 #include "lib/delay.c"
51 #include "cpu/x86/lapic/boot_cpu.c"
52 #include "northbridge/amd/amdk8/reset_test.c"
53 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
54 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
55 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
57 #define SUPERIO_GPIO_IO_BASE 0x400
59 #if USE_FAILOVER_IMAGE==0
61 #include "cpu/x86/bist.h"
63 #if CONFIG_USE_INIT == 0
64 #include "lib/memcpy.c"
67 #include "northbridge/amd/amdk8/debug.c"
69 #include "cpu/amd/mtrr/amd_earlymtrr.c"
72 #include "northbridge/amd/amdk8/setup_resource_map.c"
74 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
76 static void memreset_setup(void)
80 static void memreset(int controllers, const struct mem_controller *ctrl)
85 static void sio_gpio_setup(void){
89 /*Enable onboard scsi*/
90 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
91 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
92 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
96 static inline void activate_spd_rom(const struct mem_controller *ctrl)
101 static inline int spd_read_byte(unsigned device, unsigned address)
103 return smbus_read_byte(device, address);
107 #include "northbridge/amd/amdk8/raminit.c"
108 #include "northbridge/amd/amdk8/coherent_ht.c"
109 #include "sdram/generic_sdram.c"
111 /* tyan does not want the default */
112 #include "resourcemap.c"
114 #include "cpu/amd/dualcore/dualcore.c"
117 #define CK804B_BUSN 0x80
118 #define CK804_USE_NIC 1
119 #define CK804_USE_ACI 1
121 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
123 //set GPIO to input mode
124 #define CK804_MB_SETUP \
125 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
126 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
127 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
128 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
129 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
130 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
132 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
134 #include "cpu/amd/car/copy_and_run.c"
136 #include "cpu/amd/car/post_cache_as_ram.c"
138 #include "cpu/amd/model_fxx/init_cpus.c"
142 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
144 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
145 #include "northbridge/amd/amdk8/early_ht.c"
148 static void sio_setup(void)
156 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
158 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
160 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
162 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
163 dword |= (1<<29)|(1<<0);
164 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
166 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
168 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
170 lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
171 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
173 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
177 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
179 unsigned last_boot_normal_x = last_boot_normal();
181 /* Is this a cpu only reset? or Is this a secondary cpu? */
182 if ((cpu_init_detectedx) || (!boot_cpu())) {
183 if (last_boot_normal_x) {
190 /* Nothing special needs to be done to find bus 0 */
191 /* Allow the HT devices to be found */
193 enumerate_ht_chain();
197 /* Setup the ck804 */
200 /* Is this a deliberate reset by the bios */
202 if (bios_reset_detected() && last_boot_normal_x) {
205 /* This is the primary cpu how should I boot? */
206 else if (do_normal_boot()) {
214 __asm__ volatile ("jmp __normal_image"
216 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
221 #if HAVE_FAILOVER_BOOT==1
222 __asm__ volatile ("jmp __fallback_image"
224 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
230 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
232 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
234 #if HAVE_FAILOVER_BOOT==1
235 #if USE_FAILOVER_IMAGE==1
236 failover_process(bist, cpu_init_detectedx);
238 real_main(bist, cpu_init_detectedx);
241 #if USE_FALLBACK_IMAGE == 1
242 failover_process(bist, cpu_init_detectedx);
244 real_main(bist, cpu_init_detectedx);
248 #if USE_FAILOVER_IMAGE==0
250 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
252 static const uint16_t spd_addr [] = {
253 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
254 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
255 #if CONFIG_MAX_PHYSICAL_CPUS > 1
256 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
257 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
262 unsigned bsp_apicid = 0;
264 struct mem_controller ctrl[8];
268 bsp_apicid = init_cpus(cpu_init_detectedx);
273 lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
277 /* Halt if there was a built in self test failure */
278 report_bist_failure(bist);
282 setup_mb_resource_map();
284 dump_pci_device(PCI_DEV(0, 0x18, 0));
285 dump_pci_device(PCI_DEV(0, 0x19, 0));
288 needs_reset = setup_coherent_ht_domain();
290 wait_all_core0_started();
291 #if CONFIG_LOGICAL_CPUS==1
292 // It is said that we should start core1 after all core0 launched
294 wait_all_other_cores_started(bsp_apicid);
297 needs_reset |= ht_setup_chains_x();
299 needs_reset |= ck804_early_setup_x();
302 print_info("ht reset -\r\n");
306 allow_all_aps_stop(bsp_apicid);
309 //It's the time to set ctrl now;
310 fill_mem_ctrl(nodes, ctrl, spd_addr);
314 dump_spd_registers(&cpu[0]);
317 dump_smbus_registers();
321 sdram_initialize(nodes, ctrl);