src/mainboard/tyan/s2895/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include "northbridge/amd/amdk8/cpu_rev.c"
  17 #define K8_HT_FREQ_1G_SUPPORT 1
  18 #define K8_ALLOCATE_IO_RANGE 1
  19 //#define K8_SCAN_PCI_BUS 1
  20 #include "northbridge/amd/amdk8/incoherent_ht.c"
  21 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  22 #include "northbridge/amd/amdk8/raminit.h"
  23 #include "cpu/amd/model_fxx/apic_timer.c"
  24 #include "lib/delay.c"
  25
  26 #if CONFIG_USE_INIT == 0
  27 #include "lib/memcpy.c"
  28 #endif
  29
  30 #include "cpu/x86/lapic/boot_cpu.c"
  31 #include "northbridge/amd/amdk8/reset_test.c"
  32 #include "northbridge/amd/amdk8/debug.c"
  33 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  34
  35 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  36 #include "cpu/x86/bist.h"
  37
  38 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  39
  40 #include "northbridge/amd/amdk8/setup_resource_map.c"
  41
  42 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  43
  44 static void hard_reset(void)
  45 {
  46         set_bios_reset();
  47
  48         /* full reset */
  49         outb(0x0a, 0x0cf9);
  50         outb(0x0e, 0x0cf9);
  51 }
  52
  53 static void soft_reset(void)
  54 {
  55         set_bios_reset();
  56 #if 1
  57         /* link reset */
  58         outb(0x02, 0x0cf9);
  59         outb(0x06, 0x0cf9);
  60 #endif
  61 }
  62
  63 static void memreset_setup(void)
  64 {
  65 }
  66
  67 static void memreset(int controllers, const struct mem_controller *ctrl)
  68 {
  69 }
  70
  71 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  72
  73 #define SUPERIO_GPIO_IO_BASE 0x400
  74
  75 static void sio_gpio_setup(void){
  76
  77         unsigned value;
  78
  79 //      lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); // Already enable in failover.c
  80
  81         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  82         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  83         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  84
  85 }
  86
  87 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  88 {
  89         /* nothing to do */
  90 }
  91
  92 static inline int spd_read_byte(unsigned device, unsigned address)
  93 {
  94         return smbus_read_byte(device, address);
  95 }
  96
  97 #define K8_4RANK_DIMM_SUPPORT 1
  98
  99 #include "northbridge/amd/amdk8/raminit.c"
 100 #if 0
 101         #define ENABLE_APIC_EXT_ID 1
 102         #define APIC_ID_OFFSET 0x10
 103         #define LIFT_BSP_APIC_ID 0
 104 #else
 105         #define ENABLE_APIC_EXT_ID 0
 106 #endif
 107 #include "northbridge/amd/amdk8/coherent_ht.c"
 108 #include "sdram/generic_sdram.c"
 109
 110  /* tyan does not want the default */
 111 #include "resourcemap.c"
 112
 113 #include "cpu/amd/dualcore/dualcore.c"
 114
 115 #define FIRST_CPU  1
 116 #define SECOND_CPU 1
 117 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 118
 119 #define CK804_NUM 2
 120 #define CK804B_BUSN 0x80
 121 #define CK804_USE_NIC 1
 122 #define CK804_USE_ACI 1
 123
 124 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 125
 126 //set GPIO to input mode
 127 #define CK804_MB_SETUP \
 128                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 129                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 130                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 131                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 132                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 133                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 134
 135 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 136
 137 #include "cpu/amd/car/copy_and_run.c"
 138
 139 #include "cpu/amd/car/post_cache_as_ram.c"
 140
 141 #include "cpu/amd/model_fxx/init_cpus.c"
 142
 143 #if USE_FALLBACK_IMAGE == 1
 144
 145 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 146 #include "northbridge/amd/amdk8/early_ht.c"
 147
 148
 149 static void sio_setup(void)
 150 {
 151
 152         unsigned value;
 153         uint32_t dword;
 154         uint8_t byte;
 155
 156
 157         /* LPC Variable Range Decode 1 0x400-0x47f */
 158         /* to make sure lpc47b397 gpio on device work */
 159         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 160
 161         /* subject decoding*/
 162         byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 163         byte |= 0x20;
 164         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 165
 166         /* LPC Positive Decode 0 */
 167         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 168         /*decode VAR1, serial 0 */
 169         dword |= (1<<29)|(1<<0);
 170         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 171
 172 #if  1
 173         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 174
 175         value =  lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 176         value &= 0xbf;
 177         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 178 #endif
 179
 180 }
 181
 182 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 183
 184 void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
 185 {
 186         /* Is this a cpu only reset? */
 187         if (cpu_init_detectedx) {
 188                 if (last_boot_normal()) {
 189                         goto normal_image;
 190                 } else {
 191                         goto cpu_reset;
 192                 }
 193         }
 194
 195         /* Is this a secondary cpu? */
 196         if (!boot_cpu()) {
 197                 if (last_boot_normal()) {
 198                         goto normal_image;
 199                 } else {
 200                         goto fallback_image;
 201                 }
 202         }
 203
 204         /* Nothing special needs to be done to find bus 0 */
 205         /* Allow the HT devices to be found */
 206
 207         enumerate_ht_chain();
 208
 209         sio_setup();
 210
 211         /* Setup the ck804 */
 212         ck804_enable_rom();
 213
 214         /* Is this a deliberate reset by the bios */
 215         if (bios_reset_detected() && last_boot_normal()) {
 216                 goto normal_image;
 217         }
 218         /* This is the primary cpu how should I boot? */
 219         else if (do_normal_boot()) {
 220                 goto normal_image;
 221         }
 222         else {
 223                 goto fallback_image;
 224         }
 225  normal_image:
 226         __asm__ volatile ("jmp __normal_image"
 227                 : /* outputs */
 228                 : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 229                 );
 230  cpu_reset:
 231 #if 0
 232         //CPU reset will reset memtroller ???
 233         asm volatile ("jmp __cpu_reset"
 234                 : /* outputs */
 235                 : "a"(bist) /* inputs */
 236                 );
 237 #endif
 238
 239  fallback_image:
 240         real_main(bist, cpu_init_detectedx);
 241 }
 242 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 243 #else
 244 void amd64_main(unsigned long bist, unsigned long cpu_init_detectedx)
 245 #endif
 246 {
 247         static const struct mem_controller cpu[] = {
 248 #if FIRST_CPU
 249                 {
 250                         .node_id = 0,
 251                         .f0 = PCI_DEV(0, 0x18, 0),
 252                         .f1 = PCI_DEV(0, 0x18, 1),
 253                         .f2 = PCI_DEV(0, 0x18, 2),
 254                         .f3 = PCI_DEV(0, 0x18, 3),
 255                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 256                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 257                 },
 258 #endif
 259 #if SECOND_CPU
 260                 {
 261                         .node_id = 1,
 262                         .f0 = PCI_DEV(0, 0x19, 0),
 263                         .f1 = PCI_DEV(0, 0x19, 1),
 264                         .f2 = PCI_DEV(0, 0x19, 2),
 265                         .f3 = PCI_DEV(0, 0x19, 3),
 266                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 267                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 268                 },
 269 #endif
 270         };
 271
 272         int needs_reset;
 273
 274         unsigned cpu_reset = 0;
 275
 276         if (bist == 0) {
 277                 init_cpus(cpu_init_detectedx, sizeof(cpu)/sizeof(cpu[0]), cpu);
 278         }
 279
 280         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 281         uart_init();
 282         console_init();
 283
 284         /* Halt if there was a built in self test failure */
 285         report_bist_failure(bist);
 286
 287         setup_s2895_resource_map();
 288
 289         needs_reset = setup_coherent_ht_domain();
 290
 291         needs_reset |= ht_setup_chains_x();
 292
 293         needs_reset |= ck804_early_setup_x();
 294
 295         if (needs_reset) {
 296                 print_info("ht reset -\r\n");
 297                 soft_reset();
 298         }
 299
 300         enable_smbus();
 301
 302         memreset_setup();
 303         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 304
 305         post_cache_as_ram(cpu_reset);
 306
 307 }