src/mainboard/tyan/s2895/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #define K8_ALLOCATE_IO_RANGE 1
   5 //#define K8_SCAN_PCI_BUS 1
   6
   7 //used by raminit
   8 #define QRANK_DIMM_SUPPORT 1
   9
  10 #if CONFIG_LOGICAL_CPUS==1
  11 #define SET_NB_CFG_54 1
  12 #endif
  13
  14 #include <stdint.h>
  15 #include <device/pci_def.h>
  16 #include <arch/io.h>
  17 #include <device/pnp_def.h>
  18 #include <arch/romcc_io.h>
  19 #include <cpu/x86/lapic.h>
  20 #include "option_table.h"
  21 #include "pc80/mc146818rtc_early.c"
  22
  23 #if USE_FAILOVER_IMAGE==0
  24 #include "pc80/serial.c"
  25 #include "arch/i386/lib/console.c"
  26 #include "ram/ramtest.c"
  27
  28 #include <cpu/amd/model_fxx_rev.h>
  29
  30 #include "northbridge/amd/amdk8/incoherent_ht.c"
  31 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  32 #include "northbridge/amd/amdk8/raminit.h"
  33 #include "cpu/amd/model_fxx/apic_timer.c"
  34 #include "lib/delay.c"
  35
  36 #endif
  37
  38 #include "cpu/x86/lapic/boot_cpu.c"
  39 #include "northbridge/amd/amdk8/reset_test.c"
  40 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  41 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  42 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  43
  44 #define SUPERIO_GPIO_IO_BASE 0x400
  45
  46 #if USE_FAILOVER_IMAGE==0
  47
  48 #include "cpu/x86/bist.h"
  49
  50 #if CONFIG_USE_INIT == 0
  51 #include "lib/memcpy.c"
  52 #endif
  53
  54 #include "northbridge/amd/amdk8/debug.c"
  55
  56 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  57
  58 #include "northbridge/amd/amdk8/setup_resource_map.c"
  59
  60 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  61
  62 static void memreset_setup(void)
  63 {
  64 }
  65
  66 static void memreset(int controllers, const struct mem_controller *ctrl)
  67 {
  68 }
  69
  70 static void sio_gpio_setup(void){
  71
  72         unsigned value;
  73
  74         /*Enable onboard scsi*/
  75         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  76         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  77         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  78
  79 }
  80
  81 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  82 {
  83         /* nothing to do */
  84 }
  85
  86 static inline int spd_read_byte(unsigned device, unsigned address)
  87 {
  88         return smbus_read_byte(device, address);
  89 }
  90
  91 #include "northbridge/amd/amdk8/raminit.c"
  92 #include "northbridge/amd/amdk8/coherent_ht.c"
  93 #include "sdram/generic_sdram.c"
  94
  95  /* tyan does not want the default */
  96 #include "resourcemap.c"
  97
  98 #include "cpu/amd/dualcore/dualcore.c"
  99
 100 #define CK804_NUM 2
 101 #define CK804B_BUSN 0x80
 102 #define CK804_USE_NIC 1
 103 #define CK804_USE_ACI 1
 104
 105 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 106
 107 //set GPIO to input mode
 108 #define CK804_MB_SETUP \
 109         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 110         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 111         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 112         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 113         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 114         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 115
 116 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 117
 118 #include "cpu/amd/car/copy_and_run.c"
 119
 120 #include "cpu/amd/car/post_cache_as_ram.c"
 121
 122 #include "cpu/amd/model_fxx/init_cpus.c"
 123
 124 #endif
 125
 126 #if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
 127
 128 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 129 #include "northbridge/amd/amdk8/early_ht.c"
 130
 131 static void sio_setup(void)
 132 {
 133
 134         unsigned value;
 135         uint32_t dword;
 136         uint8_t byte;
 137
 138         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 139
 140         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 141         byte |= 0x20;
 142         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 143
 144         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 145         dword |= (1<<29)|(1<<0);
 146         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 147
 148         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xa4);
 149         dword |= (1<<16);
 150         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 151
 152         lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE);
 153         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 154         value &= 0xbf;
 155         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
 156
 157 }
 158
 159 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 160 {
 161         unsigned last_boot_normal_x = last_boot_normal();
 162
 163         /* Is this a cpu only reset? or Is this a secondary cpu? */
 164         if ((cpu_init_detectedx) || (!boot_cpu())) {
 165         if (last_boot_normal_x) {
 166         goto normal_image;
 167         } else {
 168         goto fallback_image;
 169         }
 170         }
 171
 172         /* Nothing special needs to be done to find bus 0 */
 173         /* Allow the HT devices to be found */
 174
 175         enumerate_ht_chain();
 176
 177         sio_setup();
 178
 179         /* Setup the ck804 */
 180         ck804_enable_rom();
 181
 182         /* Is this a deliberate reset by the bios */
 183 //      post_code(0x22);
 184         if (bios_reset_detected() && last_boot_normal_x) {
 185         goto normal_image;
 186         }
 187         /* This is the primary cpu how should I boot? */
 188         else if (do_normal_boot()) {
 189         goto normal_image;
 190         }
 191         else {
 192         goto fallback_image;
 193         }
 194  normal_image:
 195 //      post_code(0x23);
 196         __asm__ volatile ("jmp __normal_image"
 197         : /* outputs */
 198         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 199         );
 200
 201  fallback_image:
 202 //      post_code(0x25);
 203 #if HAVE_FAILOVER_BOOT==1
 204         __asm__ volatile ("jmp __fallback_image"
 205         : /* outputs */
 206         : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
 207         )
 208 #endif
 209         ;
 210 }
 211 #endif
 212
 213 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 214
 215 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 216 {
 217 #if HAVE_FAILOVER_BOOT==1
 218         #if USE_FAILOVER_IMAGE==1
 219         failover_process(bist, cpu_init_detectedx);
 220         #endif
 221 #else
 222         #if USE_FALLBACK_IMAGE == 1
 223         failover_process(bist, cpu_init_detectedx);
 224         #endif
 225         real_main(bist, cpu_init_detectedx);
 226 #endif
 227 }
 228
 229 #if USE_FAILOVER_IMAGE==0
 230
 231 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 232 {
 233         static const uint16_t spd_addr [] = {
 234                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 235                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 236 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 237                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 238                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 239 #endif
 240         };
 241
 242         int needs_reset;
 243         unsigned bsp_apicid = 0;
 244
 245         struct mem_controller ctrl[8];
 246         unsigned nodes;
 247
 248         if (bist == 0) {
 249                 bsp_apicid = init_cpus(cpu_init_detectedx);
 250         }
 251
 252 //      post_code(0x32);
 253
 254         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 255         uart_init();
 256         console_init();
 257
 258         /* Halt if there was a built in self test failure */
 259         report_bist_failure(bist);
 260
 261         sio_gpio_setup();
 262
 263         setup_mb_resource_map();
 264 #if 0
 265         dump_pci_device(PCI_DEV(0, 0x18, 0));
 266         dump_pci_device(PCI_DEV(0, 0x19, 0));
 267 #endif
 268
 269         needs_reset = setup_coherent_ht_domain();
 270
 271         wait_all_core0_started();
 272 #if CONFIG_LOGICAL_CPUS==1
 273         // It is said that we should start core1 after all core0 launched
 274         start_other_cores();
 275         wait_all_other_cores_started(bsp_apicid);
 276 #endif
 277
 278         needs_reset |= ht_setup_chains_x();
 279
 280         needs_reset |= ck804_early_setup_x();
 281
 282         if (needs_reset) {
 283                 print_info("ht reset -\r\n");
 284         //      soft_reset();
 285         }
 286
 287         allow_all_aps_stop(bsp_apicid);
 288
 289         nodes = get_nodes();
 290         //It's the time to set ctrl now;
 291         fill_mem_ctrl(nodes, ctrl, spd_addr);
 292
 293         enable_smbus();
 294 #if 0
 295         dump_spd_registers(&cpu[0]);
 296 #endif
 297 #if 0
 298         dump_smbus_registers();
 299 #endif
 300
 301         memreset_setup();
 302         sdram_initialize(nodes, ctrl);
 303
 304 #if 0
 305         print_pci_devices();
 306 #endif
 307
 308 #if 0
 309         dump_pci_devices();
 310 #endif
 311
 312         post_cache_as_ram();
 313 }
 314 #endif