src/mainboard/tyan/s2895/cache_as_ram_auto.c

   1 #define __ROMCC__
   2
   3 #define K8_ALLOCATE_IO_RANGE 1
   4 //#define K8_SCAN_PCI_BUS 1
   5
   6 //used by raminit
   7 #define QRANK_DIMM_SUPPORT 1
   8
   9 #if CONFIG_LOGICAL_CPUS==1
  10 #define SET_NB_CFG_54 1
  11 #endif
  12
  13 #include <stdint.h>
  14 #include <string.h>
  15 #include <device/pci_def.h>
  16 #include <arch/io.h>
  17 #include <device/pnp_def.h>
  18 #include <arch/romcc_io.h>
  19 #include <cpu/x86/lapic.h>
  20 #include "option_table.h"
  21 #include "pc80/mc146818rtc_early.c"
  22
  23 #define post_code(x) outb(x, 0x80)
  24 #include "pc80/serial.c"
  25 #include "arch/i386/lib/console.c"
  26 #include "ram/ramtest.c"
  27
  28
  29 #include <cpu/amd/model_fxx_rev.h>
  30
  31 #include "northbridge/amd/amdk8/incoherent_ht.c"
  32 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  33 #include "northbridge/amd/amdk8/raminit.h"
  34 #include "cpu/amd/model_fxx/apic_timer.c"
  35 #include "lib/delay.c"
  36
  37 #include "cpu/x86/lapic/boot_cpu.c"
  38 #include "northbridge/amd/amdk8/reset_test.c"
  39 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  40 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  41 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  42
  43 #define SUPERIO_GPIO_IO_BASE 0x400
  44
  45 #include "cpu/x86/bist.h"
  46
  47 #include "northbridge/amd/amdk8/debug.c"
  48
  49 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  50
  51 #include "northbridge/amd/amdk8/setup_resource_map.c"
  52
  53 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  54
  55 static void memreset_setup(void)
  56 {
  57 }
  58
  59 static void memreset(int controllers, const struct mem_controller *ctrl)
  60 {
  61 }
  62
  63 static void sio_gpio_setup(void){
  64
  65         unsigned value;
  66
  67         /*Enable onboard scsi*/
  68         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  69         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  70         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  71
  72 }
  73
  74 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  75 {
  76         /* nothing to do */
  77 }
  78
  79 static inline int spd_read_byte(unsigned device, unsigned address)
  80 {
  81         return smbus_read_byte(device, address);
  82 }
  83
  84 #include "northbridge/amd/amdk8/raminit.c"
  85 #include "northbridge/amd/amdk8/coherent_ht.c"
  86 #include "sdram/generic_sdram.c"
  87
  88  /* tyan does not want the default */
  89 #include "resourcemap.c"
  90
  91 #include "cpu/amd/dualcore/dualcore.c"
  92
  93 #define CK804_NUM 2
  94 #define CK804B_BUSN 0x80
  95 #define CK804_USE_NIC 1
  96 #define CK804_USE_ACI 1
  97
  98 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  99
 100 //set GPIO to input mode
 101 #define CK804_MB_SETUP \
 102         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 103         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 104         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 105         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 106         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 107         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 108
 109 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
 110
 111 #include "cpu/amd/car/copy_and_run.c"
 112
 113 #include "cpu/amd/car/post_cache_as_ram.c"
 114
 115 #include "cpu/amd/model_fxx/init_cpus.c"
 116
 117 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 118 {
 119         static const uint16_t spd_addr [] = {
 120                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 121                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 122 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 123                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 124                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 125 #endif
 126         };
 127
 128         int needs_reset;
 129         unsigned bsp_apicid = 0;
 130
 131         struct mem_controller ctrl[8];
 132         unsigned nodes;
 133
 134         if (bist == 0) {
 135                 bsp_apicid = init_cpus(cpu_init_detectedx);
 136         }
 137
 138         post_code(0x32);
 139
 140         lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 141         uart_init();
 142         console_init();
 143
 144         /* Halt if there was a built in self test failure */
 145         report_bist_failure(bist);
 146
 147         sio_gpio_setup();
 148
 149         setup_mb_resource_map();
 150 #if 0
 151         dump_pci_device(PCI_DEV(0, 0x18, 0));
 152         dump_pci_device(PCI_DEV(0, 0x19, 0));
 153 #endif
 154
 155         needs_reset = setup_coherent_ht_domain();
 156
 157         wait_all_core0_started();
 158 #if CONFIG_LOGICAL_CPUS==1
 159         // It is said that we should start core1 after all core0 launched
 160         start_other_cores();
 161         wait_all_other_cores_started(bsp_apicid);
 162 #endif
 163
 164         needs_reset |= ht_setup_chains_x();
 165
 166         needs_reset |= ck804_early_setup_x();
 167
 168         if (needs_reset) {
 169                 print_info("ht reset -\r\n");
 170         //      soft_reset();
 171         }
 172
 173         allow_all_aps_stop(bsp_apicid);
 174
 175         nodes = get_nodes();
 176         //It's the time to set ctrl now;
 177         fill_mem_ctrl(nodes, ctrl, spd_addr);
 178
 179         enable_smbus();
 180 #if 0
 181         dump_spd_registers(&cpu[0]);
 182 #endif
 183 #if 0
 184         dump_smbus_registers();
 185 #endif
 186
 187         memreset_setup();
 188         sdram_initialize(nodes, ctrl);
 189
 190 #if 0
 191         print_pci_devices();
 192 #endif
 193
 194 #if 0
 195         dump_pci_devices();
 196 #endif
 197
 198         post_cache_as_ram();
 199 }