4 #include <device/pci_def.h>
6 #include <device/pnp_def.h>
7 #include <arch/romcc_io.h>
8 #include <cpu/x86/lapic.h>
10 #include "option_table.h"
11 #include "pc80/mc146818rtc_early.c"
12 #include "pc80/serial.c"
13 #include "arch/i386/lib/console.c"
14 #include "ram/ramtest.c"
16 #include "northbridge/amd/amdk8/cpu_rev.c"
17 #define K8_HT_FREQ_1G_SUPPORT 1
18 #include "northbridge/amd/amdk8/incoherent_ht.c"
19 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
20 #include "northbridge/amd/amdk8/raminit.h"
21 #include "cpu/amd/model_fxx/apic_timer.c"
22 #include "lib/delay.c"
23 #include "cpu/x86/lapic/boot_cpu.c"
24 #include "northbridge/amd/amdk8/reset_test.c"
25 #include "northbridge/amd/amdk8/debug.c"
26 #include "cpu/amd/model_fxx/model_fxx_msr.h"
27 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
29 #include "cpu/amd/mtrr/amd_earlymtrr.c"
30 #include "cpu/x86/bist.h"
32 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
34 #include "northbridge/amd/amdk8/setup_resource_map.c"
36 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
38 static void hard_reset(void)
47 static void soft_reset(void)
57 static void memreset_setup(void)
61 static void memreset(int controllers, const struct mem_controller *ctrl)
65 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
67 #define SUPERIO_GPIO_IO_BASE 0x400
69 static void sio_gpio_setup(void){
74 /*Enable onboard scsi*/
75 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
76 value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
77 lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
82 static inline void activate_spd_rom(const struct mem_controller *ctrl)
87 static inline int spd_read_byte(unsigned device, unsigned address)
89 return smbus_read_byte(device, address);
92 #define K8_4RANK_DIMM_SUPPORT 1
94 #include "northbridge/amd/amdk8/raminit.c"
96 #define ENABLE_APIC_EXT_ID 1
97 #define APIC_ID_OFFSET 0x10
98 #define LIFT_BSP_APIC_ID 0
100 #define ENABLE_APIC_EXT_ID 0
102 #include "northbridge/amd/amdk8/coherent_ht.c"
103 #include "sdram/generic_sdram.c"
105 /* tyan does not want the default */
106 #include "resourcemap.c"
108 #if CONFIG_LOGICAL_CPUS==1
109 #define SET_NB_CFG_54 1
110 #include "cpu/amd/dualcore/dualcore.c"
112 #include "cpu/amd/model_fxx/node_id.c"
117 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
120 #define CK804B_BUSN 0xc
121 #define CK804_USE_NIC 1
122 #define CK804_USE_ACI 1
123 #include "southbridge/nvidia/ck804/ck804_early_setup.h"
124 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
126 //set GPIO to input mode
127 #define CK804_MB_SETUP \
128 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/ \
129 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
130 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
131 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/ \
132 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
133 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
135 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
138 static void main(unsigned long bist)
140 static const struct mem_controller cpu[] = {
144 .f0 = PCI_DEV(0, 0x18, 0),
145 .f1 = PCI_DEV(0, 0x18, 1),
146 .f2 = PCI_DEV(0, 0x18, 2),
147 .f3 = PCI_DEV(0, 0x18, 3),
148 .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
149 .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
155 .f0 = PCI_DEV(0, 0x19, 0),
156 .f1 = PCI_DEV(0, 0x19, 1),
157 .f2 = PCI_DEV(0, 0x19, 2),
158 .f3 = PCI_DEV(0, 0x19, 3),
159 .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
160 .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
166 #if CONFIG_LOGICAL_CPUS==1
167 struct node_core_id id;
173 /* Skip this if there was a built in self test failure */
174 amd_early_mtrr_init();
176 #if CONFIG_LOGICAL_CPUS==1
177 set_apicid_cpuid_lo();
179 id = get_node_core_id_x(); // that is initid
180 #if ENABLE_APIC_EXT_ID == 1
182 enable_apic_ext_id(id.nodeid);
186 nodeid = get_node_id();
187 #if ENABLE_APIC_EXT_ID == 1
188 enable_apic_ext_id(nodeid);
196 #if CONFIG_LOGICAL_CPUS==1
197 #if ENABLE_APIC_EXT_ID == 1
198 #if LIFT_BSP_APIC_ID == 0
201 lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
205 if (cpu_init_detected(id.nodeid)) {
206 asm volatile ("jmp __cpu_reset");
208 distinguish_cpu_resets(id.nodeid);
212 #if ENABLE_APIC_EXT_ID == 1
213 #if LIFT_BSP_APIC_ID == 0
216 lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) );
220 if (cpu_init_detected(nodeid)) {
221 asm volatile ("jmp __cpu_reset");
223 distinguish_cpu_resets(nodeid);
228 #if CONFIG_LOGICAL_CPUS==1
237 lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
241 /* Halt if there was a built in self test failure */
242 report_bist_failure(bist);
246 setup_s2895_resource_map();
248 needs_reset = setup_coherent_ht_domain();
249 #if CONFIG_LOGICAL_CPUS==1
253 needs_reset |= ht_setup_chains_x();
255 needs_reset |= ck804_early_setup_x();
258 print_info("ht reset -\r\n");
266 sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);