src/mainboard/tyan/s2895/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include <arch/cpu.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #include "northbridge/amd/amdk8/cpu_rev.c"
  17 #define K8_HT_FREQ_1G_SUPPORT 1
  18 #include "northbridge/amd/amdk8/incoherent_ht.c"
  19 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  20 #include "northbridge/amd/amdk8/raminit.h"
  21 #include "cpu/amd/model_fxx/apic_timer.c"
  22 #include "lib/delay.c"
  23 #include "cpu/x86/lapic/boot_cpu.c"
  24 #include "northbridge/amd/amdk8/reset_test.c"
  25 #include "northbridge/amd/amdk8/debug.c"
  26 #include "cpu/amd/model_fxx/model_fxx_msr.h"
  27 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
  28
  29 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  30 #include "cpu/x86/bist.h"
  31
  32 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
  37
  38 static void hard_reset(void)
  39 {
  40         set_bios_reset();
  41
  42         /* full reset */
  43         outb(0x0a, 0x0cf9);
  44         outb(0x0e, 0x0cf9);
  45 }
  46
  47 static void soft_reset(void)
  48 {
  49         set_bios_reset();
  50 #if 1
  51         /* link reset */
  52         outb(0x02, 0x0cf9);
  53         outb(0x06, 0x0cf9);
  54 #endif
  55 }
  56
  57 static void memreset_setup(void)
  58 {
  59 }
  60
  61 static void memreset(int controllers, const struct mem_controller *ctrl)
  62 {
  63 }
  64
  65 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
  66
  67 #define SUPERIO_GPIO_IO_BASE 0x400
  68
  69 static void sio_gpio_setup(void){
  70
  71         unsigned value;
  72
  73 #if 1
  74         /*Enable onboard scsi*/
  75         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
  76         value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
  77         lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
  78 #endif
  79
  80 }
  81
  82 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  83 {
  84         /* nothing to do */
  85 }
  86
  87 static inline int spd_read_byte(unsigned device, unsigned address)
  88 {
  89         return smbus_read_byte(device, address);
  90 }
  91
  92 #define K8_4RANK_DIMM_SUPPORT 1
  93
  94 #include "northbridge/amd/amdk8/raminit.c"
  95 #if 0
  96         #define ENABLE_APIC_EXT_ID 1
  97         #define APIC_ID_OFFSET 0x10
  98         #define LIFT_BSP_APIC_ID 0
  99 #else
 100         #define ENABLE_APIC_EXT_ID 0
 101 #endif
 102 #include "northbridge/amd/amdk8/coherent_ht.c"
 103 #include "sdram/generic_sdram.c"
 104
 105 /* tyan does not want the default */
 106 #include "resourcemap.c"
 107
 108 #define FIRST_CPU  1
 109 #define SECOND_CPU 1
 110 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
 111
 112 #define CK804_NUM 2
 113 #define CK804B_BUSN 0xc
 114 #define CK804_USE_NIC 1
 115 #define CK804_USE_ACI 1
 116 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
 117
 118 //set GPIO to input mode
 119 #define CK804_MB_SETUP \
 120                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 5, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M9,GPIO6, PCIXB2_PRSNT1_L*/  \
 121                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXB2_PRSNT2_L*/ \
 122                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/  \
 123                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 7, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M5,GPIO8, PCIXA_PRSNT2_L*/   \
 124                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/  \
 125                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
 126
 127 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
 128
 129
 130 static void main(unsigned long bist)
 131 {
 132         static const struct mem_controller cpu[] = {
 133 #if FIRST_CPU
 134                 {
 135                         .node_id = 0,
 136                         .f0 = PCI_DEV(0, 0x18, 0),
 137                         .f1 = PCI_DEV(0, 0x18, 1),
 138                         .f2 = PCI_DEV(0, 0x18, 2),
 139                         .f3 = PCI_DEV(0, 0x18, 3),
 140                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 141                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 142                 },
 143 #endif
 144 #if SECOND_CPU
 145                 {
 146                         .node_id = 1,
 147                         .f0 = PCI_DEV(0, 0x19, 0),
 148                         .f1 = PCI_DEV(0, 0x19, 1),
 149                         .f2 = PCI_DEV(0, 0x19, 2),
 150                         .f3 = PCI_DEV(0, 0x19, 3),
 151                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 152                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 153                 },
 154 #endif
 155         };
 156
 157         int needs_reset;
 158         unsigned nodeid;
 159
 160         if (bist == 0) {
 161                 /* Skip this if there was a built in self test failure */
 162                 amd_early_mtrr_init();
 163
 164                 nodeid = lapicid();;
 165         #if ENABLE_APIC_EXT_ID == 1
 166                 enable_apic_ext_id(nodeid);
 167         #endif
 168
 169                 enable_lapic();
 170                 init_timer();
 171
 172
 173         #if ENABLE_APIC_EXT_ID == 1
 174             #if LIFT_BSP_APIC_ID == 0
 175                 if(nodeid != 0)
 176             #endif
 177                         lapic_write(LAPIC_ID, ( lapic_read(LAPIC_ID) | (APIC_ID_OFFSET<<24) ) ); // CPU apicid is from 0x10
 178
 179         #endif
 180
 181                 if (cpu_init_detected(nodeid)) {
 182                         asm volatile ("jmp __cpu_reset");
 183                 }
 184                 distinguish_cpu_resets(nodeid);
 185
 186
 187                 if (!boot_cpu()
 188                 ) {
 189                         stop_this_cpu(); // it will stop all cores except core0 of cpu0
 190                 }
 191         }
 192
 193
 194         lpc47b397_enable_serial(SERIAL_DEV, TTYS0_BASE);
 195         uart_init();
 196         console_init();
 197
 198         /* Halt if there was a built in self test failure */
 199         report_bist_failure(bist);
 200
 201         sio_gpio_setup();
 202
 203         setup_s2895_resource_map();
 204
 205         needs_reset = setup_coherent_ht_domain();
 206
 207         needs_reset |= ht_setup_chains_x();
 208
 209         needs_reset |= ck804_early_setup_x();
 210
 211         if (needs_reset) {
 212                 print_info("ht reset -\r\n");
 213                 soft_reset();
 214         }
 215
 216
 217         enable_smbus();
 218
 219         memreset_setup();
 220         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 221
 222
 223 }