4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
6 uses USE_FAILOVER_IMAGE
7 uses HAVE_FAILOVER_BOOT
10 uses HAVE_OPTION_TABLE
12 uses CONFIG_MAX_PHYSICAL_CPUS
13 uses CONFIG_LOGICAL_CPUS
22 uses ROM_SECTION_OFFSET
23 uses CONFIG_ROM_PAYLOAD
24 uses CONFIG_ROM_PAYLOAD_START
25 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
26 uses CONFIG_PRECOMPRESSED_PAYLOAD
34 uses LB_CKS_RANGE_START
44 uses MAINBOARD_PART_NUMBER
46 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
47 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
48 uses COREBOOT_EXTRA_VERSION
58 uses DEFAULT_CONSOLE_LOGLEVEL
59 uses MAXIMUM_CONSOLE_LOGLEVEL
60 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
61 uses CONFIG_CONSOLE_SERIAL8250
64 uses CONFIG_CONSOLE_VGA
65 uses CONFIG_VGA_ROM_RUN
66 uses CONFIG_PCI_ROM_RUN
67 uses HW_MEM_HOLE_SIZEK
68 uses K8_HT_FREQ_1G_SUPPORT
74 uses CONFIG_USE_PRINTK_IN_CAR
78 uses ENABLE_APIC_EXT_ID
82 uses HT_CHAIN_UNITID_BASE
83 uses HT_CHAIN_END_UNITID_BASE
84 uses SB_HT_CHAIN_ON_BUS0
85 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
87 uses CONFIG_LB_MEM_TOPK
89 ## ROM_SIZE is the size of boot ROM that this board will use.
90 default ROM_SIZE=1024*1024
93 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
95 #default FALLBACK_SIZE=131072
96 #default FALLBACK_SIZE=0x40000
99 default FALLBACK_SIZE=0x3f000
101 default FAILOVER_SIZE=0x01000
104 default CONFIG_LB_MEM_TOPK=2048
107 ## Build code for the fallback boot
109 default HAVE_FALLBACK_BOOT=1
110 default HAVE_FAILOVER_BOOT=1
113 ## Build code to reset the motherboard from coreboot
115 default HAVE_HARD_RESET=1
120 default HAVE_SMI_HANDLER=0
123 ## Build code to export a programmable irq routing table
125 default HAVE_PIRQ_TABLE=1
126 default IRQ_SLOT_COUNT=11
129 ## Build code to export an x86 MP table
130 ## Useful for specifying IRQ routing values
132 default HAVE_MP_TABLE=1
135 ## Build code to provide ACPI support
137 default HAVE_ACPI_TABLES=1
138 default HAVE_LOW_TABLES=1
139 default HAVE_HIGH_TABLES=1
140 default CONFIG_MULTIBOOT=0
143 ## Build code to export a CMOS option table
145 default HAVE_OPTION_TABLE=1
148 ## Move the default coreboot cmos range off of AMD RTC registers
150 default LB_CKS_RANGE_START=49
151 default LB_CKS_RANGE_END=122
152 default LB_CKS_LOC=123
155 default CONFIG_CONSOLE_VGA=1
156 default CONFIG_PCI_ROM_RUN=1
157 default CONFIG_VGA_ROM_RUN=1
160 ## Build code for SMP support
161 ## Only worry about 2 micro processors
164 default CONFIG_MAX_CPUS=4
165 default CONFIG_MAX_PHYSICAL_CPUS=2
166 default CONFIG_LOGICAL_CPUS=1
168 default SERIAL_CPU_INIT=0
171 default HW_MEM_HOLE_SIZEK=0x100000
173 ##HT Unit ID offset, default is 1, the typical one
174 default HT_CHAIN_UNITID_BASE=0x0
176 ##real SB Unit ID, default is 0x20, mean dont touch it at last
177 #default HT_CHAIN_END_UNITID_BASE=0x0
179 #make the SB HT chain on bus 0, default is not (0)
180 default SB_HT_CHAIN_ON_BUS0=2
182 ##only offset for SB chain?, default is yes(1)
183 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
185 #Opteron K8 1G HT Support
186 default K8_HT_FREQ_1G_SUPPORT=1
189 default CONFIG_CONSOLE_VGA=1
190 default CONFIG_PCI_ROM_RUN=1
193 ## enable CACHE_AS_RAM specifics
195 default USE_DCACHE_RAM=1
196 default DCACHE_RAM_BASE=0xcf000
197 default DCACHE_RAM_SIZE=0x1000
198 default CONFIG_USE_INIT=0
200 default ENABLE_APIC_EXT_ID=0
201 default APIC_ID_OFFSET=0x10
202 default LIFT_BSP_APIC_ID=0
206 ## Build code to setup a generic IOAPIC
208 default CONFIG_IOAPIC=1
211 ## Clean up the motherboard id strings
213 default MAINBOARD_PART_NUMBER="s2895"
214 default MAINBOARD_VENDOR="Tyan"
215 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
216 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
219 ### coreboot layout values
222 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
223 default ROM_IMAGE_SIZE = 65536
226 ## Use a small 8K stack
228 default STACK_SIZE=0x2000
231 ## Use a small 16K heap
233 default HEAP_SIZE=0x4000
236 ## Only use the option table in a normal image
238 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
241 ## Coreboot C code runs at this location in RAM
243 default _RAMBASE=0x00100000
246 ## Load the payload from the ROM
248 default CONFIG_ROM_PAYLOAD = 1
251 ### Defaults of options that you may want to override in the target config file
255 ## The default compiler
257 default CC="$(CROSS_COMPILE)gcc -m32"
261 ## Disable the gdb stub by default
263 default CONFIG_GDB_STUB=0
265 default CONFIG_USE_PRINTK_IN_CAR=1
268 ## The Serial Console
271 # To Enable the Serial Console
272 default CONFIG_CONSOLE_SERIAL8250=1
274 ## Select the serial console baud rate
275 default TTYS0_BAUD=115200
276 #default TTYS0_BAUD=57600
277 #default TTYS0_BAUD=38400
278 #default TTYS0_BAUD=19200
279 #default TTYS0_BAUD=9600
280 #default TTYS0_BAUD=4800
281 #default TTYS0_BAUD=2400
282 #default TTYS0_BAUD=1200
284 # Select the serial console base port
285 default TTYS0_BASE=0x3f8
287 # Select the serial protocol
288 # This defaults to 8 data bits, 1 stop bit, and no parity
289 default TTYS0_LCS=0x3
292 ### Select the coreboot loglevel
294 ## EMERG 1 system is unusable
295 ## ALERT 2 action must be taken immediately
296 ## CRIT 3 critical conditions
297 ## ERR 4 error conditions
298 ## WARNING 5 warning conditions
299 ## NOTICE 6 normal but significant condition
300 ## INFO 7 informational
301 ## DEBUG 8 debug-level messages
302 ## SPEW 9 Way too many details
304 ## Request this level of debugging output
305 default DEFAULT_CONSOLE_LOGLEVEL=8
306 ## At a maximum only compile in this level of debugging
307 default MAXIMUM_CONSOLE_LOGLEVEL=8
310 ## Select power on after power fail setting
311 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
318 default CONFIG_CBFS=0