3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
5 uses USE_FAILOVER_IMAGE
6 uses HAVE_FAILOVER_BOOT
11 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_LOGICAL_CPUS
21 uses ROM_SECTION_OFFSET
22 uses CONFIG_ROM_PAYLOAD
23 uses CONFIG_ROM_PAYLOAD_START
24 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
25 uses CONFIG_PRECOMPRESSED_PAYLOAD
33 uses LB_CKS_RANGE_START
37 uses HAVE_MAINBOARD_RESOURCES
43 uses MAINBOARD_PART_NUMBER
45 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
46 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
47 uses COREBOOT_EXTRA_VERSION
57 uses DEFAULT_CONSOLE_LOGLEVEL
58 uses MAXIMUM_CONSOLE_LOGLEVEL
59 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
60 uses CONFIG_CONSOLE_SERIAL8250
64 uses CONFIG_CONSOLE_VGA
65 uses CONFIG_VGA_ROM_RUN
66 uses CONFIG_PCI_ROM_RUN
67 uses HW_MEM_HOLE_SIZEK
68 uses K8_HT_FREQ_1G_SUPPORT
74 uses CONFIG_USE_PRINTK_IN_CAR
78 uses ENABLE_APIC_EXT_ID
82 uses HT_CHAIN_UNITID_BASE
83 uses HT_CHAIN_END_UNITID_BASE
84 uses SB_HT_CHAIN_ON_BUS0
85 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
87 uses CONFIG_LB_MEM_TOPK
89 ## ROM_SIZE is the size of boot ROM that this board will use.
90 default ROM_SIZE=1024*1024
93 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
95 #default FALLBACK_SIZE=131072
96 #default FALLBACK_SIZE=0x40000
99 default FALLBACK_SIZE=0x3f000
101 default FAILOVER_SIZE=0x01000
104 default CONFIG_LB_MEM_TOPK=2048
107 ## Build code for the fallback boot
109 default HAVE_FALLBACK_BOOT=1
110 default HAVE_FAILOVER_BOOT=1
113 ## Build code to reset the motherboard from coreboot
115 default HAVE_HARD_RESET=1
120 default HAVE_SMI_HANDLER=0
123 ## Build code to export a programmable irq routing table
125 default HAVE_PIRQ_TABLE=1
126 default IRQ_SLOT_COUNT=11
129 ## Build code to export an x86 MP table
130 ## Useful for specifying IRQ routing values
132 default HAVE_MP_TABLE=1
135 ## Build code to provide ACPI support
137 default HAVE_ACPI_TABLES=1
138 default HAVE_LOW_TABLES=1
139 default HAVE_MAINBOARD_RESOURCES=1
140 default HAVE_HIGH_TABLES=0
141 default CONFIG_MULTIBOOT=0
144 ## Build code to export a CMOS option table
146 default HAVE_OPTION_TABLE=1
149 ## Move the default coreboot cmos range off of AMD RTC registers
151 default LB_CKS_RANGE_START=49
152 default LB_CKS_RANGE_END=122
153 default LB_CKS_LOC=123
156 default CONFIG_CONSOLE_VGA=1
157 default CONFIG_PCI_ROM_RUN=1
158 default CONFIG_VGA_ROM_RUN=1
161 ## Build code for SMP support
162 ## Only worry about 2 micro processors
165 default CONFIG_MAX_CPUS=4
166 default CONFIG_MAX_PHYSICAL_CPUS=2
167 default CONFIG_LOGICAL_CPUS=1
169 default SERIAL_CPU_INIT=0
172 #default CONFIG_CHIP_NAME=1
175 default HW_MEM_HOLE_SIZEK=0x100000
177 ##HT Unit ID offset, default is 1, the typical one
178 default HT_CHAIN_UNITID_BASE=0x0
180 ##real SB Unit ID, default is 0x20, mean dont touch it at last
181 #default HT_CHAIN_END_UNITID_BASE=0x0
183 #make the SB HT chain on bus 0, default is not (0)
184 default SB_HT_CHAIN_ON_BUS0=2
186 ##only offset for SB chain?, default is yes(1)
187 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
189 #Opteron K8 1G HT Support
190 default K8_HT_FREQ_1G_SUPPORT=1
193 default CONFIG_CONSOLE_VGA=1
194 default CONFIG_PCI_ROM_RUN=1
197 ## enable CACHE_AS_RAM specifics
199 default USE_DCACHE_RAM=1
200 default DCACHE_RAM_BASE=0xcf000
201 default DCACHE_RAM_SIZE=0x1000
202 default CONFIG_USE_INIT=0
204 default ENABLE_APIC_EXT_ID=0
205 default APIC_ID_OFFSET=0x10
206 default LIFT_BSP_APIC_ID=0
210 ## Build code to setup a generic IOAPIC
212 default CONFIG_IOAPIC=1
215 ## Clean up the motherboard id strings
217 default MAINBOARD_PART_NUMBER="s2895"
218 default MAINBOARD_VENDOR="Tyan"
219 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
220 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
223 ### coreboot layout values
226 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
227 default ROM_IMAGE_SIZE = 65536
230 ## Use a small 8K stack
232 default STACK_SIZE=0x2000
235 ## Use a small 16K heap
237 default HEAP_SIZE=0x4000
240 ## Only use the option table in a normal image
242 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
245 ## Coreboot C code runs at this location in RAM
247 default _RAMBASE=0x00100000
250 ## Load the payload from the ROM
252 default CONFIG_ROM_PAYLOAD = 1
255 ### Defaults of options that you may want to override in the target config file
259 ## The default compiler
261 default CC="$(CROSS_COMPILE)gcc -m32"
265 ## Disable the gdb stub by default
267 default CONFIG_GDB_STUB=0
269 default CONFIG_USE_PRINTK_IN_CAR=1
272 ## The Serial Console
275 # To Enable the Serial Console
276 default CONFIG_CONSOLE_SERIAL8250=1
278 ## Select the serial console baud rate
279 default TTYS0_BAUD=115200
280 #default TTYS0_BAUD=57600
281 #default TTYS0_BAUD=38400
282 #default TTYS0_BAUD=19200
283 #default TTYS0_BAUD=9600
284 #default TTYS0_BAUD=4800
285 #default TTYS0_BAUD=2400
286 #default TTYS0_BAUD=1200
288 # Select the serial console base port
289 default TTYS0_BASE=0x3f8
291 # Select the serial protocol
292 # This defaults to 8 data bits, 1 stop bit, and no parity
293 default TTYS0_LCS=0x3
296 ### Select the coreboot loglevel
298 ## EMERG 1 system is unusable
299 ## ALERT 2 action must be taken immediately
300 ## CRIT 3 critical conditions
301 ## ERR 4 error conditions
302 ## WARNING 5 warning conditions
303 ## NOTICE 6 normal but significant condition
304 ## INFO 7 informational
305 ## DEBUG 8 debug-level messages
306 ## SPEW 9 Way too many details
308 ## Request this level of debugging output
309 default DEFAULT_CONSOLE_LOGLEVEL=8
310 ## At a maximum only compile in this level of debugging
311 default MAXIMUM_CONSOLE_LOGLEVEL=8
314 ## Select power on after power fail setting
315 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"