1 uses CONFIG_HAVE_MP_TABLE
2 uses CONFIG_HAVE_PIRQ_TABLE
3 uses CONFIG_USE_FALLBACK_IMAGE
4 uses CONFIG_HAVE_FALLBACK_BOOT
5 uses CONFIG_USE_FAILOVER_IMAGE
6 uses CONFIG_HAVE_FAILOVER_BOOT
7 uses CONFIG_HAVE_HARD_RESET
8 uses CONFIG_IRQ_SLOT_COUNT
9 uses CONFIG_HAVE_OPTION_TABLE
11 uses CONFIG_MAX_PHYSICAL_CPUS
12 uses CONFIG_LOGICAL_CPUS
15 uses CONFIG_FALLBACK_SIZE
16 uses CONFIG_FAILOVER_SIZE
18 uses CONFIG_ROM_SECTION_SIZE
19 uses CONFIG_ROM_IMAGE_SIZE
20 uses CONFIG_ROM_SECTION_SIZE
21 uses CONFIG_ROM_SECTION_OFFSET
22 uses CONFIG_ROM_PAYLOAD
23 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
24 uses CONFIG_PRECOMPRESSED_PAYLOAD
26 uses CONFIG_XIP_ROM_SIZE
27 uses CONFIG_XIP_ROM_BASE
28 uses CONFIG_STACK_SIZE
30 uses CONFIG_USE_OPTION_TABLE
31 uses CONFIG_LB_CKS_RANGE_START
32 uses CONFIG_LB_CKS_RANGE_END
33 uses CONFIG_LB_CKS_LOC
34 uses CONFIG_HAVE_ACPI_TABLES
35 uses CONFIG_HAVE_ACPI_RESUME
36 uses CONFIG_HAVE_LOW_TABLES
38 uses CONFIG_HAVE_SMI_HANDLER
40 uses CONFIG_MAINBOARD_PART_NUMBER
41 uses CONFIG_MAINBOARD_VENDOR
42 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
43 uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
44 uses COREBOOT_EXTRA_VERSION
47 uses CONFIG_CROSS_COMPILE
51 uses CONFIG_TTYS0_BAUD
52 uses CONFIG_TTYS0_BASE
54 uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
55 uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
56 uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
57 uses CONFIG_CONSOLE_SERIAL8250
58 uses CONFIG_HAVE_INIT_TIMER
60 uses CONFIG_CONSOLE_VGA
61 uses CONFIG_VGA_ROM_RUN
62 uses CONFIG_PCI_ROM_RUN
63 uses CONFIG_HW_MEM_HOLE_SIZEK
64 uses CONFIG_K8_HT_FREQ_1G_SUPPORT
66 uses CONFIG_USE_DCACHE_RAM
67 uses CONFIG_DCACHE_RAM_BASE
68 uses CONFIG_DCACHE_RAM_SIZE
70 uses CONFIG_USE_PRINTK_IN_CAR
72 uses CONFIG_SERIAL_CPU_INIT
74 uses CONFIG_ENABLE_APIC_EXT_ID
75 uses CONFIG_APIC_ID_OFFSET
76 uses CONFIG_LIFT_BSP_APIC_ID
78 uses CONFIG_HT_CHAIN_UNITID_BASE
79 uses CONFIG_HT_CHAIN_END_UNITID_BASE
80 uses CONFIG_SB_HT_CHAIN_ON_BUS0
81 uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
83 uses CONFIG_LB_MEM_TOPK
85 ## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
86 default CONFIG_ROM_SIZE=1024*1024
89 ## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
93 default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
95 default CONFIG_FAILOVER_SIZE=0x01000
98 default CONFIG_LB_MEM_TOPK=2048
101 ## Build code for the fallback boot
103 default CONFIG_HAVE_FALLBACK_BOOT=1
104 default CONFIG_HAVE_FAILOVER_BOOT=1
107 ## Build code to reset the motherboard from coreboot
109 default CONFIG_HAVE_HARD_RESET=1
114 default CONFIG_HAVE_SMI_HANDLER=0
117 ## Build code to export a programmable irq routing table
119 default CONFIG_HAVE_PIRQ_TABLE=1
120 default CONFIG_IRQ_SLOT_COUNT=11
123 ## Build code to export an x86 MP table
124 ## Useful for specifying IRQ routing values
126 default CONFIG_HAVE_MP_TABLE=1
129 ## Build code to provide ACPI support
131 default CONFIG_HAVE_ACPI_TABLES=1
132 default CONFIG_HAVE_LOW_TABLES=1
133 default CONFIG_MULTIBOOT=0
136 ## Build code to export a CMOS option table
138 default CONFIG_HAVE_OPTION_TABLE=1
141 ## Move the default coreboot cmos range off of AMD RTC registers
143 default CONFIG_LB_CKS_RANGE_START=49
144 default CONFIG_LB_CKS_RANGE_END=122
145 default CONFIG_LB_CKS_LOC=123
148 default CONFIG_CONSOLE_VGA=1
149 default CONFIG_PCI_ROM_RUN=1
150 default CONFIG_VGA_ROM_RUN=1
153 ## Build code for SMP support
154 ## Only worry about 2 micro processors
157 default CONFIG_MAX_CPUS=4
158 default CONFIG_MAX_PHYSICAL_CPUS=2
159 default CONFIG_LOGICAL_CPUS=1
161 default CONFIG_SERIAL_CPU_INIT=0
164 default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
166 ##HT Unit ID offset, default is 1, the typical one
167 default CONFIG_HT_CHAIN_UNITID_BASE=0x0
169 ##real SB Unit ID, default is 0x20, mean dont touch it at last
170 #default CONFIG_HT_CHAIN_END_UNITID_BASE=0x0
172 #make the SB HT chain on bus 0, default is not (0)
173 default CONFIG_SB_HT_CHAIN_ON_BUS0=2
175 ##only offset for SB chain?, default is yes(1)
176 default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
178 #Opteron K8 1G HT Support
179 default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
182 default CONFIG_CONSOLE_VGA=1
183 default CONFIG_PCI_ROM_RUN=1
186 ## enable CACHE_AS_RAM specifics
188 default CONFIG_USE_DCACHE_RAM=1
189 default CONFIG_DCACHE_RAM_BASE=0xcf000
190 default CONFIG_DCACHE_RAM_SIZE=0x1000
191 default CONFIG_USE_INIT=0
193 default CONFIG_ENABLE_APIC_EXT_ID=0
194 default CONFIG_APIC_ID_OFFSET=0x10
195 default CONFIG_LIFT_BSP_APIC_ID=0
199 ## Build code to setup a generic IOAPIC
201 default CONFIG_IOAPIC=1
204 ## Clean up the motherboard id strings
206 default CONFIG_MAINBOARD_PART_NUMBER="s2895"
207 default CONFIG_MAINBOARD_VENDOR="Tyan"
208 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
209 default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2895
212 ### coreboot layout values
215 ## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
216 default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
219 ## Use a small 8K stack
221 default CONFIG_STACK_SIZE=0x2000
224 ## Use a small 16K heap
226 default CONFIG_HEAP_SIZE=0x4000
229 ## Only use the option table in a normal image
231 default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
234 ## Coreboot C code runs at this location in RAM
236 default CONFIG_RAMBASE=0x00100000
239 ## Load the payload from the ROM
241 default CONFIG_ROM_PAYLOAD = 1
244 ### Defaults of options that you may want to override in the target config file
248 ## The default compiler
250 default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
254 ## Disable the gdb stub by default
256 default CONFIG_GDB_STUB=0
258 default CONFIG_USE_PRINTK_IN_CAR=1
261 ## The Serial Console
264 # To Enable the Serial Console
265 default CONFIG_CONSOLE_SERIAL8250=1
267 ## Select the serial console baud rate
268 default CONFIG_TTYS0_BAUD=115200
269 #default CONFIG_TTYS0_BAUD=57600
270 #default CONFIG_TTYS0_BAUD=38400
271 #default CONFIG_TTYS0_BAUD=19200
272 #default CONFIG_TTYS0_BAUD=9600
273 #default CONFIG_TTYS0_BAUD=4800
274 #default CONFIG_TTYS0_BAUD=2400
275 #default CONFIG_TTYS0_BAUD=1200
277 # Select the serial console base port
278 default CONFIG_TTYS0_BASE=0x3f8
280 # Select the serial protocol
281 # This defaults to 8 data bits, 1 stop bit, and no parity
282 default CONFIG_TTYS0_LCS=0x3
285 ### Select the coreboot loglevel
287 ## EMERG 1 system is unusable
288 ## ALERT 2 action must be taken immediately
289 ## CRIT 3 critical conditions
290 ## ERR 4 error conditions
291 ## WARNING 5 warning conditions
292 ## NOTICE 6 normal but significant condition
293 ## INFO 7 informational
294 ## CONFIG_DEBUG 8 debug-level messages
295 ## SPEW 9 Way too many details
297 ## Request this level of debugging output
298 default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
299 ## At a maximum only compile in this level of debugging
300 default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
303 ## Select power on after power fail setting
304 default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"