src/mainboard/tyan/s2895/Config.lb

   1 ##
   2 ## Compute the location and size of where this firmware image
   3 ## (linuxBIOS plus bootloader) will live in the boot rom chip.
   4 ##
   5 if USE_FAILOVER_IMAGE
   6         default ROM_SECTION_SIZE   = FAILOVER_SIZE
   7         default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
   8 else
   9     if USE_FALLBACK_IMAGE
  10         default ROM_SECTION_SIZE   = FALLBACK_SIZE
  11         default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  12     else
  13         default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
  14         default ROM_SECTION_OFFSET = 0
  15     end
  16 end
  17
  18 ##
  19 ## Compute the start location and size size of
  20 ## The linuxBIOS bootloader.
  21 ##
  22 default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
  23 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
  24
  25 ##
  26 ## Compute where this copy of linuxBIOS will start in the boot rom
  27 ##
  28 default _ROMBASE      = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
  29
  30 ##
  31 ## Compute a range of ROM that can cached to speed up linuxBIOS,
  32 ## execution speed.
  33 ##
  34 ## XIP_ROM_SIZE must be a power of 2.
  35 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
  36 ##
  37 default XIP_ROM_SIZE=65536
  38
  39 if USE_FAILOVER_IMAGE
  40         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  41 else
  42     if USE_FALLBACK_IMAGE
  43         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
  44     else
  45         default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
  46     end
  47 end
  48
  49 arch i386 end
  50
  51 ##
  52 ## Build the objects we have code for in this directory.
  53 ##
  54
  55 driver mainboard.o
  56 #needed by irq_tables and mptable and acpi_tables
  57 object get_bus_conf.o
  58
  59 if HAVE_MP_TABLE object mptable.o end
  60 if HAVE_PIRQ_TABLE object irq_tables.o end
  61 #object reset.o
  62 if USE_DCACHE_RAM
  63
  64         if CONFIG_USE_INIT
  65                 makerule ./auto.o
  66                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  67                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
  68                 end
  69         else
  70                 makerule ./auto.inc
  71                         depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
  72                         action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
  73                         action "perl -e 's/.rodata/.rom.data/g' -pi $@"
  74                         action "perl -e 's/.text/.section .rom.text/g' -pi $@"
  75                 end
  76         end
  77
  78 else
  79         ##
  80         ## Romcc output
  81         ##
  82         makerule ./failover.E
  83                 depends "$(MAINBOARD)/failover.c ./romcc"
  84                 action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  85         end
  86
  87         makerule ./failover.inc
  88                 depends "$(MAINBOARD)/failover.c ./romcc"
  89                 action "./romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
  90         end
  91
  92         makerule ./auto.E
  93                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  94                 action  "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
  95         end
  96
  97         makerule ./auto.inc
  98                 depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
  99                 action  "./romcc    -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
 100         end
 101
 102 end
 103
 104 ##
 105 ## Build our 16 bit and 32 bit linuxBIOS entry code
 106 ##
 107 if HAVE_FAILOVER_BOOT
 108     if USE_FAILOVER_IMAGE
 109         mainboardinit cpu/x86/16bit/entry16.inc
 110         ldscript /cpu/x86/16bit/entry16.lds
 111     end
 112 else
 113     if USE_FALLBACK_IMAGE
 114         mainboardinit cpu/x86/16bit/entry16.inc
 115         ldscript /cpu/x86/16bit/entry16.lds
 116     end
 117 end
 118
 119 mainboardinit cpu/x86/32bit/entry32.inc
 120
 121 if USE_DCACHE_RAM
 122         if CONFIG_USE_INIT
 123                 ldscript /cpu/x86/32bit/entry32.lds
 124         end
 125
 126         if CONFIG_USE_INIT
 127                 ldscript /cpu/amd/car/cache_as_ram.lds
 128         end
 129 end
 130
 131
 132 ##
 133 ## Build our reset vector (This is where linuxBIOS is entered)
 134 ##
 135 if HAVE_FAILOVER_BOOT
 136     if USE_FAILOVER_IMAGE
 137         mainboardinit cpu/x86/16bit/reset16.inc
 138         ldscript /cpu/x86/16bit/reset16.lds
 139     else
 140         mainboardinit cpu/x86/32bit/reset32.inc
 141         ldscript /cpu/x86/32bit/reset32.lds
 142     end
 143 else
 144     if USE_FALLBACK_IMAGE
 145         mainboardinit cpu/x86/16bit/reset16.inc
 146         ldscript /cpu/x86/16bit/reset16.lds
 147     else
 148         mainboardinit cpu/x86/32bit/reset32.inc
 149         ldscript /cpu/x86/32bit/reset32.lds
 150     end
 151 end
 152
 153 if USE_DCACHE_RAM
 154 else
 155         ### Should this be in the northbridge code?
 156         mainboardinit arch/i386/lib/cpu_reset.inc
 157 end
 158
 159 ##
 160 ## Include an id string (For safe flashing)
 161 ##
 162 mainboardinit southbridge/nvidia/ck804/id.inc
 163 ldscript /southbridge/nvidia/ck804/id.lds
 164
 165 ##
 166 ## ROMSTRAP table for CK804
 167 ##
 168 if HAVE_FAILOVER_BOOT
 169     if USE_FAILOVER_IMAGE
 170         mainboardinit southbridge/nvidia/ck804/romstrap.inc
 171         ldscript /southbridge/nvidia/ck804/romstrap.lds
 172     end
 173 else
 174     if USE_FALLBACK_IMAGE
 175         mainboardinit southbridge/nvidia/ck804/romstrap.inc
 176         ldscript /southbridge/nvidia/ck804/romstrap.lds
 177     end
 178 end
 179
 180 if USE_DCACHE_RAM
 181         ##
 182         ## Setup Cache-As-Ram
 183         ##
 184         mainboardinit cpu/amd/car/cache_as_ram.inc
 185 end
 186
 187 ###
 188 ### This is the early phase of linuxBIOS startup
 189 ### Things are delicate and we test to see if we should
 190 ### failover to another image.
 191 ###
 192 if HAVE_FAILOVER_BOOT
 193     if USE_FAILOVER_IMAGE
 194         if USE_DCACHE_RAM
 195                 ldscript /arch/i386/lib/failover_failover.lds
 196         end
 197     end
 198 else
 199     if USE_FALLBACK_IMAGE
 200         if USE_DCACHE_RAM
 201                 ldscript /arch/i386/lib/failover.lds
 202         else
 203                 mainboardinit ./failover.inc
 204         end
 205     end
 206 end
 207
 208 ##
 209 ## Setup RAM
 210 ##
 211 if USE_DCACHE_RAM
 212
 213         if CONFIG_USE_INIT
 214                 initobject auto.o
 215         else
 216                 mainboardinit ./auto.inc
 217         end
 218
 219 else
 220         # ROMCC
 221         mainboardinit cpu/x86/fpu/enable_fpu.inc
 222         mainboardinit cpu/x86/mmx/enable_mmx.inc
 223         mainboardinit cpu/x86/sse/enable_sse.inc
 224         mainboardinit ./auto.inc
 225         mainboardinit cpu/x86/sse/disable_sse.inc
 226         mainboardinit cpu/x86/mmx/disable_mmx.inc
 227
 228 end
 229
 230 ##
 231 ## Include the secondary Configuration files
 232 ##
 233 if CONFIG_CHIP_NAME
 234         config chip.h
 235 end
 236
 237 # sample config for tyan/s2895
 238 chip northbridge/amd/amdk8/root_complex
 239         device apic_cluster 0 on
 240                 chip cpu/amd/socket_940
 241                         device apic 0 on end
 242                 end
 243         end
 244         device pci_domain 0 on
 245                 chip northbridge/amd/amdk8 #mc0
 246                         device pci 18.0 on
 247                                 #  devices on link 0, link 0 == LDT 0
 248                                 chip southbridge/nvidia/ck804
 249                                         device pci 0.0 on end   # HT
 250                                         device pci 1.0 on # LPC
 251                                                 chip superio/smsc/lpc47b397
 252                                                         device pnp 2e.0 on #  Floppy
 253                                                                  io 0x60 = 0x3f0
 254                                                                 irq 0x70 = 6
 255                                                                 drq 0x74 = 2
 256                                                         end
 257                                                         device pnp 2e.3 off #  Parallel Port
 258                                                                  io 0x60 = 0x378
 259                                                                 irq 0x70 = 7
 260                                                         end
 261                                                         device pnp 2e.4 on #  Com1
 262                                                                 io 0x60 = 0x3f8
 263                                                                 irq 0x70 = 4
 264                                                         end
 265                                                         device pnp 2e.5 off #  Com2
 266                                                                 io 0x60 = 0x2f8
 267                                                                 irq 0x70 = 3
 268                                                         end
 269                                                         device pnp 2e.7 on #  Keyboard
 270                                                                 io 0x60 = 0x60
 271                                                                 io 0x62 = 0x64
 272                                                                 irq 0x70 = 1
 273                                                                 irq 0x72 = 12
 274                                                         end
 275                                                         device pnp 2e.8 on # HW Monitor
 276                                                                 io 0x60 = 0x290
 277                                                                 chip drivers/generic/generic # LM95221 CPU temp
 278                                                                         device i2c 2b on end
 279                                                                 end
 280                                                                 chip drivers/generic/generic # EMCT03
 281                                                                         device i2c 54 on end
 282                                                                 end
 283                                                         end
 284                                                         device  pnp 2e.a on #  RT
 285                                                                 io 0x60 = 0x400
 286                                                         end
 287                                                 end
 288                                         end
 289                                         device pci 1.1 on # SM 0
 290                                                 chip drivers/generic/generic #dimm 0-0-0
 291                                                         device i2c 50 on end
 292                                                 end
 293                                                 chip drivers/generic/generic #dimm 0-0-1
 294                                                         device i2c 51 on end
 295                                                 end
 296                                                 chip drivers/generic/generic #dimm 0-1-0
 297                                                         device i2c 52 on end
 298                                                 end
 299                                                 chip drivers/generic/generic #dimm 0-1-1
 300                                                         device i2c 53 on end
 301                                                 end
 302                                                 chip drivers/generic/generic #dimm 1-0-0
 303                                                         device i2c 54 on end
 304                                                 end
 305                                                 chip drivers/generic/generic #dimm 1-0-1
 306                                                         device i2c 55 on end
 307                                                 end
 308                                                 chip drivers/generic/generic #dimm 1-1-0
 309                                                         device i2c 56 on end
 310                                                 end
 311                                                 chip drivers/generic/generic #dimm 1-1-1
 312                                                         device i2c 57 on end
 313                                                 end
 314                                         end # SM
 315                                         device pci 1.1 on # SM 1
 316 #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus?
 317 #                                                chip drivers/generic/generic #PCIXA Slot1
 318 #                                                        device i2c 50 on end
 319 #                                                end
 320 #                                                chip drivers/generic/generic #PCIXB Slot1
 321 #                                                        device i2c 51 on end
 322 #                                                end
 323 #                                                chip drivers/generic/generic #PCIXB Slot2
 324 #                                                        device i2c 52 on end
 325 #                                                end
 326 #                                                chip drivers/generic/generic #PCI Slot1
 327 #                                                        device i2c 53 on end
 328 #                                                end
 329 #                                                chip drivers/generic/generic #Master CK804 PCI-E
 330 #                                                        device i2c 54 on end
 331 #                                                end
 332 #                                                chip drivers/generic/generic #Slave CK804 PCI-E
 333 #                                                        device i2c 55 on end
 334 #                                                end
 335                                                 chip drivers/generic/generic #MAC EEPROM
 336                                                         device i2c 51 on end
 337                                                 end
 338
 339                                         end # SM
 340                                         device pci 2.0 on end # USB 1.1
 341                                         device pci 2.1 on end # USB 2
 342                                         device pci 4.0 on end # ACI
 343                                         device pci 4.1 off end # MCI
 344                                         device pci 6.0 on end # IDE
 345                                         device pci 7.0 on end # SATA 1
 346                                         device pci 8.0 on end # SATA 0
 347                                         device pci 9.0 on end # PCI
 348                                         device pci a.0 on end # NIC
 349                                         device pci b.0 off end # PCI E 3
 350                                         device pci c.0 off end # PCI E 2
 351                                         device pci d.0 off end # PCI E 1
 352                                         device pci e.0 on end # PCI E 0
 353                                         register "ide0_enable" = "1"
 354                                         register "ide1_enable" = "1"
 355                                         register "sata0_enable" = "1"
 356                                         register "sata1_enable" = "1"
 357 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 358 #                                       register "raid_rom_address" = "0xfff90000"
 359                                         register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
 360                                         register "mac_eeprom_addr" = "0x51"
 361                                 end
 362                         end #  device pci 18.0
 363                         device pci 18.0 on end # Link 1
 364                         device pci 18.0 on
 365                         #  devices on link 2, link 2 == LDT 2
 366                                 chip southbridge/amd/amd8131
 367                                         # the on/off keyword is mandatory
 368                                         device pci 0.0 on end
 369                                         device pci 0.1 on end
 370                                         device pci 1.0 on
 371                                                 chip drivers/pci/onboard
 372                                                         device pci 6.0 on end # lsi scsi
 373                                                         device pci 6.1 on end
 374                                                 end
 375                                         end
 376                                         device pci 1.1 on end
 377                                 end
 378                         end # device pci 18.0
 379                         device pci 18.1 on end
 380                         device pci 18.2 on end
 381                         device pci 18.3 on end
 382                 end # mc0
 383
 384                 chip northbridge/amd/amdk8
 385                         device pci 19.0 on #  northbridge
 386                                 #  devices on link 0, link 0 == LDT 0
 387                                 chip southbridge/nvidia/ck804
 388                                         device pci 0.0 on end   # HT
 389                                         device pci 1.0 on end   # LPC
 390                                         device pci 1.1 off end # SM
 391                                         device pci 2.0 off end # USB 1.1
 392                                         device pci 2.1 off end # USB 2
 393                                         device pci 4.0 off end # ACI
 394                                         device pci 4.1 off end # MCI
 395                                         device pci 6.0 off end # IDE
 396                                         device pci 7.0 off end # SATA 1
 397                                         device pci 8.0 off end # SATA 0
 398                                         device pci 9.0 off end # PCI
 399                                         device pci a.0 on end # NIC
 400                                         device pci b.0 off end # PCI E 3
 401                                         device pci c.0 off end # PCI E 2
 402                                         device pci d.0 off end # PCI E 1
 403                                         device pci e.0 on end # PCI E 0
 404 #                                       register "nic_rom_address" = "0xfff80000" # 64k
 405                                         register "mac_eeprom_smbus" = "3"
 406                                         register "mac_eeprom_addr" = "0x51"
 407                                 end
 408                         end #  device pci 19.0
 409
 410                         device pci 19.0 on end
 411                         device pci 19.0 on end
 412                         device pci 19.1 on end
 413                         device pci 19.2 on end
 414                         device pci 19.3 on end
 415                 end
 416         end # PCI domain
 417
 418 #       chip drivers/generic/debug
 419 #               device pnp 0.0 off end # chip name
 420 #                device pnp 0.1 off end # pci_regs_all
 421 #                device pnp 0.2 off end # mem
 422 #                device pnp 0.3 off end # cpuid
 423 #                device pnp 0.4 on end # smbus_regs_all
 424 #                device pnp 0.5 off end # dual core msr
 425 #                device pnp 0.6 off end # cache size
 426 #                device pnp 0.7 off end # tsc
 427 #       end
 428 end #root_complex