1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/failovercalculation.lb
8 ## Build the objects we have code for in this directory.
12 #needed by irq_tables and mptable and acpi_tables
15 if CONFIG_HAVE_MP_TABLE object mptable.o end
16 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
19 if CONFIG_HAVE_ACPI_TABLES
22 depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
23 action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
24 action "mv dsdt.hex dsdt.c"
27 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
28 #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
33 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
34 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
38 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
39 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
40 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
41 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
46 ## Build our 16 bit and 32 bit coreboot entry code
48 if CONFIG_HAVE_FAILOVER_BOOT
49 if CONFIG_USE_FAILOVER_IMAGE
50 mainboardinit cpu/x86/16bit/entry16.inc
51 ldscript /cpu/x86/16bit/entry16.lds
54 if CONFIG_USE_FALLBACK_IMAGE
55 mainboardinit cpu/x86/16bit/entry16.inc
56 ldscript /cpu/x86/16bit/entry16.lds
60 mainboardinit cpu/x86/32bit/entry32.inc
63 ldscript /cpu/x86/32bit/entry32.lds
67 ldscript /cpu/amd/car/cache_as_ram.lds
71 ## Build our reset vector (This is where coreboot is entered)
73 if CONFIG_HAVE_FAILOVER_BOOT
74 if CONFIG_USE_FAILOVER_IMAGE
75 mainboardinit cpu/x86/16bit/reset16.inc
76 ldscript /cpu/x86/16bit/reset16.lds
78 mainboardinit cpu/x86/32bit/reset32.inc
79 ldscript /cpu/x86/32bit/reset32.lds
82 if CONFIG_USE_FALLBACK_IMAGE
83 mainboardinit cpu/x86/16bit/reset16.inc
84 ldscript /cpu/x86/16bit/reset16.lds
86 mainboardinit cpu/x86/32bit/reset32.inc
87 ldscript /cpu/x86/32bit/reset32.lds
92 ## Include an id string (For safe flashing)
94 mainboardinit southbridge/nvidia/ck804/id.inc
95 ldscript /southbridge/nvidia/ck804/id.lds
98 ## ROMSTRAP table for CK804
100 if CONFIG_HAVE_FAILOVER_BOOT
101 if CONFIG_USE_FAILOVER_IMAGE
102 mainboardinit southbridge/nvidia/ck804/romstrap.inc
103 ldscript /southbridge/nvidia/ck804/romstrap.lds
106 if CONFIG_USE_FALLBACK_IMAGE
107 mainboardinit southbridge/nvidia/ck804/romstrap.inc
108 ldscript /southbridge/nvidia/ck804/romstrap.lds
113 ## Setup Cache-As-Ram
115 mainboardinit cpu/amd/car/cache_as_ram.inc
118 ### This is the early phase of coreboot startup
119 ### Things are delicate and we test to see if we should
120 ### failover to another image.
122 if CONFIG_HAVE_FAILOVER_BOOT
123 if CONFIG_USE_FAILOVER_IMAGE
124 ldscript /arch/i386/lib/failover_failover.lds
127 if CONFIG_USE_FALLBACK_IMAGE
128 ldscript /arch/i386/lib/failover.lds
138 mainboardinit ./auto.inc
142 ## Include the secondary Configuration files
146 include devicetree.cb