src/mainboard/tyan/s2892/romstage.c

   1 #include <stdint.h>
   2 #include <string.h>
   3 #include <device/pci_def.h>
   4 #include <arch/io.h>
   5 #include <device/pnp_def.h>
   6 #include <arch/romcc_io.h>
   7 #include <cpu/x86/lapic.h>
   8 #include <pc80/mc146818rtc.h>
   9
  10 #include <console/console.h>
  11 #include <lib.h>
  12
  13 #include <cpu/amd/model_fxx_rev.h>
  14
  15 #include "northbridge/amd/amdk8/incoherent_ht.c"
  16 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  17 #include "northbridge/amd/amdk8/raminit.h"
  18 #include "cpu/amd/model_fxx/apic_timer.c"
  19 #include "lib/delay.c"
  20
  21 #include "cpu/x86/lapic/boot_cpu.c"
  22 #include "northbridge/amd/amdk8/reset_test.c"
  23 #include "northbridge/amd/amdk8/debug.c"
  24 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  25
  26 #include "cpu/x86/mtrr/earlymtrr.c"
  27 #include "cpu/x86/bist.h"
  28
  29 #include "northbridge/amd/amdk8/setup_resource_map.c"
  30
  31 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  32
  33 static void memreset(int controllers, const struct mem_controller *ctrl)
  34 {
  35 }
  36
  37 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  38 {
  39         /* nothing to do */
  40 }
  41
  42 static inline int spd_read_byte(unsigned device, unsigned address)
  43 {
  44         return smbus_read_byte(device, address);
  45 }
  46
  47 #include "northbridge/amd/amdk8/raminit.c"
  48 #include "northbridge/amd/amdk8/coherent_ht.c"
  49 #include "lib/generic_sdram.c"
  50
  51  /* tyan does not want the default */
  52 #include "resourcemap.c"
  53
  54 #include "cpu/amd/dualcore/dualcore.c"
  55
  56 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  57 //set GPIO to input mode
  58 #define CK804_MB_SETUP \
  59         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  60         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  61         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  62         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  63
  64 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  65
  66
  67
  68 #include "cpu/amd/car/post_cache_as_ram.c"
  69
  70 #include "cpu/amd/model_fxx/init_cpus.c"
  71
  72 #include "northbridge/amd/amdk8/early_ht.c"
  73
  74 static void sio_setup(void)
  75 {
  76         uint32_t dword;
  77         uint8_t byte;
  78
  79         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  80         byte |= 0x20;
  81         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  82
  83         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  84         dword |= (1<<0);
  85         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  86 }
  87
  88 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  89 {
  90         static const uint16_t spd_addr [] = {
  91                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  92                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  93 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  94                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
  95                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
  96 #endif
  97         };
  98
  99         int needs_reset;
 100         unsigned bsp_apicid = 0;
 101
 102         struct mem_controller ctrl[8];
 103         unsigned nodes;
 104
 105         if (!cpu_init_detectedx && boot_cpu()) {
 106                 /* Nothing special needs to be done to find bus 0 */
 107                 /* Allow the HT devices to be found */
 108
 109                 enumerate_ht_chain();
 110
 111                 sio_setup();
 112         }
 113
 114         if (bist == 0) {
 115                 bsp_apicid = init_cpus(cpu_init_detectedx);
 116         }
 117
 118 //      post_code(0x32);
 119
 120         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 121         uart_init();
 122         console_init();
 123
 124         /* Halt if there was a built in self test failure */
 125         report_bist_failure(bist);
 126
 127         setup_mb_resource_map();
 128
 129         needs_reset = setup_coherent_ht_domain();
 130
 131         wait_all_core0_started();
 132 #if CONFIG_LOGICAL_CPUS==1
 133         // It is said that we should start core1 after all core0 launched
 134         start_other_cores();
 135         wait_all_other_cores_started(bsp_apicid);
 136 #endif
 137
 138         needs_reset |= ht_setup_chains_x();
 139
 140         needs_reset |= ck804_early_setup_x();
 141
 142         if (needs_reset) {
 143                 printk(BIOS_INFO, "ht reset -\n");
 144                 soft_reset();
 145         }
 146
 147         allow_all_aps_stop(bsp_apicid);
 148
 149         nodes = get_nodes();
 150         //It's the time to set ctrl now;
 151         fill_mem_ctrl(nodes, ctrl, spd_addr);
 152
 153         enable_smbus();
 154
 155         sdram_initialize(nodes, ctrl);
 156
 157         post_cache_as_ram();
 158 }
 159