src/mainboard/tyan/s2892/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 #define QRANK_DIMM_SUPPORT 1
   5
   6 #if CONFIG_LOGICAL_CPUS==1
   7 #define SET_NB_CFG_54 1
   8 #endif
   9
  10 #include <stdint.h>
  11 #include <string.h>
  12 #include <device/pci_def.h>
  13 #include <arch/io.h>
  14 #include <device/pnp_def.h>
  15 #include <arch/romcc_io.h>
  16 #include <cpu/x86/lapic.h>
  17 #include "option_table.h"
  18 #include "pc80/mc146818rtc_early.c"
  19
  20 #define post_code(x) outb(x, 0x80)
  21 #include "pc80/serial.c"
  22 #include "arch/i386/lib/console.c"
  23 #include "lib/ramtest.c"
  24
  25 #include <cpu/amd/model_fxx_rev.h>
  26
  27 #include "northbridge/amd/amdk8/incoherent_ht.c"
  28 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  29 #include "northbridge/amd/amdk8/raminit.h"
  30 #include "cpu/amd/model_fxx/apic_timer.c"
  31 #include "lib/delay.c"
  32
  33 #include "cpu/x86/lapic/boot_cpu.c"
  34 #include "northbridge/amd/amdk8/reset_test.c"
  35 #include "northbridge/amd/amdk8/debug.c"
  36 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  37
  38 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  39 #include "cpu/x86/bist.h"
  40
  41 #include "northbridge/amd/amdk8/setup_resource_map.c"
  42
  43 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  44
  45 static void memreset(int controllers, const struct mem_controller *ctrl)
  46 {
  47 }
  48
  49 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  50 {
  51         /* nothing to do */
  52 }
  53
  54 static inline int spd_read_byte(unsigned device, unsigned address)
  55 {
  56         return smbus_read_byte(device, address);
  57 }
  58
  59 #include "northbridge/amd/amdk8/raminit.c"
  60 #include "northbridge/amd/amdk8/coherent_ht.c"
  61 #include "lib/generic_sdram.c"
  62
  63  /* tyan does not want the default */
  64 #include "resourcemap.c"
  65
  66 #include "cpu/amd/dualcore/dualcore.c"
  67
  68 #define CK804_NUM 1
  69 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  70 //set GPIO to input mode
  71 #define CK804_MB_SETUP \
  72         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  73         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  74         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  75         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  76
  77 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  78
  79 #include "cpu/amd/car/copy_and_run.c"
  80
  81 #include "cpu/amd/car/post_cache_as_ram.c"
  82
  83 #include "cpu/amd/model_fxx/init_cpus.c"
  84
  85 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  86 #include "northbridge/amd/amdk8/early_ht.c"
  87
  88 static void sio_setup(void)
  89 {
  90         uint32_t dword;
  91         uint8_t byte;
  92
  93         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  94         byte |= 0x20;
  95         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  96
  97         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  98         dword |= (1<<0);
  99         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 100 }
 101
 102 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 103 {
 104         static const uint16_t spd_addr [] = {
 105                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 106                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 107 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 108                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 109                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 110 #endif
 111         };
 112
 113         int needs_reset;
 114         unsigned bsp_apicid = 0;
 115
 116         struct mem_controller ctrl[8];
 117         unsigned nodes;
 118
 119         if (!((cpu_init_detectedx) || (!boot_cpu()))) {
 120                 /* Nothing special needs to be done to find bus 0 */
 121                 /* Allow the HT devices to be found */
 122
 123                 enumerate_ht_chain();
 124
 125                 sio_setup();
 126
 127                 /* Setup the ck804 */
 128                 ck804_enable_rom();
 129         }
 130
 131         if (bist == 0) {
 132                 bsp_apicid = init_cpus(cpu_init_detectedx);
 133         }
 134
 135 //      post_code(0x32);
 136
 137         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 138         uart_init();
 139         console_init();
 140
 141         /* Halt if there was a built in self test failure */
 142         report_bist_failure(bist);
 143
 144         setup_mb_resource_map();
 145
 146         needs_reset = setup_coherent_ht_domain();
 147
 148         wait_all_core0_started();
 149 #if CONFIG_LOGICAL_CPUS==1
 150         // It is said that we should start core1 after all core0 launched
 151         start_other_cores();
 152         wait_all_other_cores_started(bsp_apicid);
 153 #endif
 154
 155         needs_reset |= ht_setup_chains_x();
 156
 157         needs_reset |= ck804_early_setup_x();
 158
 159         if (needs_reset) {
 160                 printk_info("ht reset -\n");
 161                 soft_reset();
 162         }
 163
 164         allow_all_aps_stop(bsp_apicid);
 165
 166         nodes = get_nodes();
 167         //It's the time to set ctrl now;
 168         fill_mem_ctrl(nodes, ctrl, spd_addr);
 169
 170         enable_smbus();
 171
 172         sdram_initialize(nodes, ctrl);
 173
 174         post_cache_as_ram();
 175 }