src/mainboard/tyan/s2892/romstage.c

   1 #define QRANK_DIMM_SUPPORT 1
   2
   3 #if CONFIG_LOGICAL_CPUS==1
   4 #define SET_NB_CFG_54 1
   5 #endif
   6
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <device/pci_def.h>
  10 #include <arch/io.h>
  11 #include <device/pnp_def.h>
  12 #include <arch/romcc_io.h>
  13 #include <cpu/x86/lapic.h>
  14 #include "option_table.h"
  15 #include "pc80/mc146818rtc_early.c"
  16
  17 #include "pc80/serial.c"
  18 #include "console/console.c"
  19 #include "lib/ramtest.c"
  20
  21 #include <cpu/amd/model_fxx_rev.h>
  22
  23 #include "northbridge/amd/amdk8/incoherent_ht.c"
  24 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  25 #include "northbridge/amd/amdk8/raminit.h"
  26 #include "cpu/amd/model_fxx/apic_timer.c"
  27 #include "lib/delay.c"
  28
  29 #include "cpu/x86/lapic/boot_cpu.c"
  30 #include "northbridge/amd/amdk8/reset_test.c"
  31 #include "northbridge/amd/amdk8/debug.c"
  32 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  33
  34 #include "cpu/x86/mtrr/earlymtrr.c"
  35 #include "cpu/x86/bist.h"
  36
  37 #include "northbridge/amd/amdk8/setup_resource_map.c"
  38
  39 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  40
  41 static void memreset(int controllers, const struct mem_controller *ctrl)
  42 {
  43 }
  44
  45 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  46 {
  47         /* nothing to do */
  48 }
  49
  50 static inline int spd_read_byte(unsigned device, unsigned address)
  51 {
  52         return smbus_read_byte(device, address);
  53 }
  54
  55 #include "northbridge/amd/amdk8/raminit.c"
  56 #include "northbridge/amd/amdk8/coherent_ht.c"
  57 #include "lib/generic_sdram.c"
  58
  59  /* tyan does not want the default */
  60 #include "resourcemap.c"
  61
  62 #include "cpu/amd/dualcore/dualcore.c"
  63
  64 #define CK804_NUM 1
  65 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  66 //set GPIO to input mode
  67 #define CK804_MB_SETUP \
  68         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  69         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  70         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  71         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  72
  73 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  74
  75
  76
  77 #include "cpu/amd/car/post_cache_as_ram.c"
  78
  79 #include "cpu/amd/model_fxx/init_cpus.c"
  80
  81 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  82 #include "northbridge/amd/amdk8/early_ht.c"
  83
  84 static void sio_setup(void)
  85 {
  86         uint32_t dword;
  87         uint8_t byte;
  88
  89         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  90         byte |= 0x20;
  91         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  92
  93         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  94         dword |= (1<<0);
  95         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  96 }
  97
  98 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  99 {
 100         static const uint16_t spd_addr [] = {
 101                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 102                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 103 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 104                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 105                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 106 #endif
 107         };
 108
 109         int needs_reset;
 110         unsigned bsp_apicid = 0;
 111
 112         struct mem_controller ctrl[8];
 113         unsigned nodes;
 114
 115         if (!cpu_init_detectedx && boot_cpu()) {
 116                 /* Nothing special needs to be done to find bus 0 */
 117                 /* Allow the HT devices to be found */
 118
 119                 enumerate_ht_chain();
 120
 121                 sio_setup();
 122
 123                 /* Setup the ck804 */
 124                 ck804_enable_rom();
 125         }
 126
 127         if (bist == 0) {
 128                 bsp_apicid = init_cpus(cpu_init_detectedx);
 129         }
 130
 131 //      post_code(0x32);
 132
 133         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 134         uart_init();
 135         console_init();
 136
 137         /* Halt if there was a built in self test failure */
 138         report_bist_failure(bist);
 139
 140         setup_mb_resource_map();
 141
 142         needs_reset = setup_coherent_ht_domain();
 143
 144         wait_all_core0_started();
 145 #if CONFIG_LOGICAL_CPUS==1
 146         // It is said that we should start core1 after all core0 launched
 147         start_other_cores();
 148         wait_all_other_cores_started(bsp_apicid);
 149 #endif
 150
 151         needs_reset |= ht_setup_chains_x();
 152
 153         needs_reset |= ck804_early_setup_x();
 154
 155         if (needs_reset) {
 156                 printk(BIOS_INFO, "ht reset -\n");
 157                 soft_reset();
 158         }
 159
 160         allow_all_aps_stop(bsp_apicid);
 161
 162         nodes = get_nodes();
 163         //It's the time to set ctrl now;
 164         fill_mem_ctrl(nodes, ctrl, spd_addr);
 165
 166         enable_smbus();
 167
 168         sdram_initialize(nodes, ctrl);
 169
 170         post_cache_as_ram();
 171 }
 172