src/mainboard/tyan/s2892/romstage.c

   1
   2 #if CONFIG_LOGICAL_CPUS==1
   3 #define SET_NB_CFG_54 1
   4 #endif
   5
   6 #include <stdint.h>
   7 #include <string.h>
   8 #include <device/pci_def.h>
   9 #include <arch/io.h>
  10 #include <device/pnp_def.h>
  11 #include <arch/romcc_io.h>
  12 #include <cpu/x86/lapic.h>
  13 #include <pc80/mc146818rtc.h>
  14
  15 #include <console/console.h>
  16 #include <lib.h>
  17
  18 #include <cpu/amd/model_fxx_rev.h>
  19
  20 #include "northbridge/amd/amdk8/incoherent_ht.c"
  21 #include "southbridge/nvidia/ck804/ck804_early_smbus.h"
  22 #include "northbridge/amd/amdk8/raminit.h"
  23 #include "cpu/amd/model_fxx/apic_timer.c"
  24 #include "lib/delay.c"
  25
  26 #include "cpu/x86/lapic/boot_cpu.c"
  27 #include "northbridge/amd/amdk8/reset_test.c"
  28 #include "northbridge/amd/amdk8/debug.c"
  29 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  30
  31 #include "cpu/x86/mtrr/earlymtrr.c"
  32 #include "cpu/x86/bist.h"
  33
  34 #include "northbridge/amd/amdk8/setup_resource_map.c"
  35
  36 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  37
  38 static void memreset(int controllers, const struct mem_controller *ctrl)
  39 {
  40 }
  41
  42 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  43 {
  44         /* nothing to do */
  45 }
  46
  47 static inline int spd_read_byte(unsigned device, unsigned address)
  48 {
  49         return smbus_read_byte(device, address);
  50 }
  51
  52 #include "northbridge/amd/amdk8/raminit.c"
  53 #include "northbridge/amd/amdk8/coherent_ht.c"
  54 #include "lib/generic_sdram.c"
  55
  56  /* tyan does not want the default */
  57 #include "resourcemap.c"
  58
  59 #include "cpu/amd/dualcore/dualcore.c"
  60
  61 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  62 //set GPIO to input mode
  63 #define CK804_MB_SETUP \
  64         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  65         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  66         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  67         RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  68
  69 #include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
  70
  71
  72
  73 #include "cpu/amd/car/post_cache_as_ram.c"
  74
  75 #include "cpu/amd/model_fxx/init_cpus.c"
  76
  77 #include "northbridge/amd/amdk8/early_ht.c"
  78
  79 static void sio_setup(void)
  80 {
  81         uint32_t dword;
  82         uint8_t byte;
  83
  84         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  85         byte |= 0x20;
  86         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  87
  88         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  89         dword |= (1<<0);
  90         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  91 }
  92
  93 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
  94 {
  95         static const uint16_t spd_addr [] = {
  96                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
  97                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
  98 #if CONFIG_MAX_PHYSICAL_CPUS > 1
  99                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 100                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 101 #endif
 102         };
 103
 104         int needs_reset;
 105         unsigned bsp_apicid = 0;
 106
 107         struct mem_controller ctrl[8];
 108         unsigned nodes;
 109
 110         if (!cpu_init_detectedx && boot_cpu()) {
 111                 /* Nothing special needs to be done to find bus 0 */
 112                 /* Allow the HT devices to be found */
 113
 114                 enumerate_ht_chain();
 115
 116                 sio_setup();
 117         }
 118
 119         if (bist == 0) {
 120                 bsp_apicid = init_cpus(cpu_init_detectedx);
 121         }
 122
 123 //      post_code(0x32);
 124
 125         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 126         uart_init();
 127         console_init();
 128
 129         /* Halt if there was a built in self test failure */
 130         report_bist_failure(bist);
 131
 132         setup_mb_resource_map();
 133
 134         needs_reset = setup_coherent_ht_domain();
 135
 136         wait_all_core0_started();
 137 #if CONFIG_LOGICAL_CPUS==1
 138         // It is said that we should start core1 after all core0 launched
 139         start_other_cores();
 140         wait_all_other_cores_started(bsp_apicid);
 141 #endif
 142
 143         needs_reset |= ht_setup_chains_x();
 144
 145         needs_reset |= ck804_early_setup_x();
 146
 147         if (needs_reset) {
 148                 printk(BIOS_INFO, "ht reset -\n");
 149                 soft_reset();
 150         }
 151
 152         allow_all_aps_stop(bsp_apicid);
 153
 154         nodes = get_nodes();
 155         //It's the time to set ctrl now;
 156         fill_mem_ctrl(nodes, ctrl, spd_addr);
 157
 158         enable_smbus();
 159
 160         sdram_initialize(nodes, ctrl);
 161
 162         post_cache_as_ram();
 163 }
 164