1 #include <console/console.h>
2 #include <arch/smp/mpspec.h>
3 #include <device/pci.h>
6 #include <cpu/amd/amdk8_sysconf.h>
8 extern unsigned char bus_isa;
9 extern unsigned char bus_ck804_0; //1
10 extern unsigned char bus_ck804_1; //2
11 extern unsigned char bus_ck804_2; //3
12 extern unsigned char bus_ck804_3; //4
13 extern unsigned char bus_ck804_4; //5
14 extern unsigned char bus_ck804_5; //6
15 extern unsigned char bus_8131_0; //7
16 extern unsigned char bus_8131_1; //8
17 extern unsigned char bus_8131_2; //9
18 extern unsigned apicid_ck804;
19 extern unsigned apicid_8131_1;
20 extern unsigned apicid_8131_2;
22 extern unsigned sbdn3;
24 static void *smp_write_config_table(void *v)
26 struct mp_config_table *mc;
28 unsigned char bus_num;
31 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
33 mptable_init(mc, "S2892 ", LAPIC_ADDR);
35 smp_write_processors(mc);
41 /* define bus and isa numbers */
42 for(bus_num = 0; bus_num < bus_isa; bus_num++) {
43 smp_write_bus(mc, bus_num, "PCI ");
45 smp_write_bus(mc, bus_isa, "ISA ");
47 /*I/O APICs: APIC ID Version State Address*/
53 dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x1,0));
55 res = find_resource(dev, PCI_BASE_ADDRESS_1);
57 smp_write_ioapic(mc, apicid_ck804, 0x11, res->base);
60 /* Initialize interrupt mapping*/
63 pci_write_config32(dev, 0x7c, dword);
66 pci_write_config32(dev, 0x80, dword);
69 pci_write_config32(dev, 0x84, dword);
73 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,1));
75 res = find_resource(dev, PCI_BASE_ADDRESS_0);
77 smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
80 dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,1));
82 res = find_resource(dev, PCI_BASE_ADDRESS_0);
84 smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
90 mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 1);
92 /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
93 // Onboard ck804 smbus
94 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+1)<<2)|1, apicid_ck804, 0xa); // 10
96 // Onboard ck804 USB 1.1
97 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|0, apicid_ck804, 0x15); // 21
99 // Onboard ck804 USB 2
100 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn+2)<<2)|1, apicid_ck804, 0x14); // 20
102 // Onboard ck804 SATA 0
103 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +7)<<2)|0, apicid_ck804, 0x17); // 23
105 // Onboard ck804 SATA 1
106 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((sbdn +8)<<2)|0, apicid_ck804, 0x16); // 22
110 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|i, apicid_ck804, 0x10 + (2+i+4-sbdn%4)%4);
115 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_4, (0x00<<2)|i, apicid_ck804, 0x10 + (1+i+4-sbdn%4)%4);
121 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (0x04<<2)|i, apicid_ck804, 0x10 + (0+i)%4); //16
126 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (6<<2)|0, apicid_ck804, 0x12); // 18
127 //Onboard intel 10/100
128 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_1, (8<<2)|0, apicid_ck804, 0x12); // 18
133 //Onboard Broadcom NIC
135 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (9<<2)|i, apicid_8131_2, (0+i)%4); //28
140 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (7<<2)|i, apicid_8131_2, (0+i)%4); //28
143 //Slot 4 PCIX 133/100/66
145 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|i, apicid_8131_2, (2+i)%4); //30
151 //Slot 5 PCIX 133/100/66
153 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|i, apicid_8131_1, (3+i)%4); //27
157 //Slot 6 PCIX 133/100/66
159 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|i, apicid_8131_1, (2+i)%4); //26
162 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
163 smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
164 smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
165 /* There is no extension information... */
167 /* Compute the checksums */
168 mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
169 mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
170 printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n",
171 mc, smp_next_mpe_entry(mc));
172 return smp_next_mpe_entry(mc);
175 unsigned long write_smp_table(unsigned long addr)
178 v = smp_write_floating_table(addr);
179 return (unsigned long)smp_write_config_table(v);