3 #include <device/pci_def.h>
4 #include <device/pci_ids.h>
6 #include <arch/romcc_io.h>
7 #include <cpu/x86/lapic.h>
8 #include "pc80/mc146818rtc_early.c"
10 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
11 #include "northbridge/amd/amdk8/early_ht.c"
12 #include "cpu/x86/lapic/boot_cpu.c"
13 #include "cpu/x86/mtrr/earlymtrr.c"
14 #include "northbridge/amd/amdk8/reset_test.c"
16 static void sio_setup(void)
23 byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
25 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
27 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
29 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
34 #if CONFIG_LOGICAL_CPUS==1
35 #include "cpu/amd/dualcore/dualcore_id.c"
38 static unsigned long main(unsigned long bist)
40 /* Make cerain my local apic is useable */
43 /* Is this a cpu only reset? */
44 if (early_mtrr_init_detected()) {
45 if (last_boot_normal()) {
52 /* Is this a secondary cpu? */
54 if (last_boot_normal()) {
61 /* Nothing special needs to be done to find bus 0 */
62 /* Allow the HT devices to be found */
71 /* Is this a deliberate reset by the bios */
72 if (bios_reset_detected() && last_boot_normal()) {
75 /* This is the primary cpu how should I boot? */
76 else if (do_normal_boot()) {
83 asm volatile ("jmp __normal_image"
85 : "a" (bist) /* inputs */