src/mainboard/tyan/s2892/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <device/pci_def.h>
   6 #include <arch/io.h>
   7 #include <device/pnp_def.h>
   8 #include <arch/romcc_io.h>
   9 #include <cpu/x86/lapic.h>
  10 #include "option_table.h"
  11 #include "pc80/mc146818rtc_early.c"
  12 #include "pc80/serial.c"
  13 #include "arch/i386/lib/console.c"
  14 #include "ram/ramtest.c"
  15
  16 #if 0
  17 static void post_code(uint8_t value) {
  18 #if 1
  19         int i;
  20         for(i=0;i<0x80000;i++) {
  21                 outb(value, 0x80);
  22         }
  23 #endif
  24 }
  25 #endif
  26
  27 #include <cpu/amd/model_fxx_rev.h>
  28 #include "northbridge/amd/amdk8/incoherent_ht.c"
  29 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  30 #include "northbridge/amd/amdk8/raminit.h"
  31 #include "cpu/amd/model_fxx/apic_timer.c"
  32 #include "lib/delay.c"
  33
  34 #if CONFIG_USE_INIT == 0
  35 #include "lib/memcpy.c"
  36 #endif
  37
  38 #include "cpu/x86/lapic/boot_cpu.c"
  39 #include "northbridge/amd/amdk8/reset_test.c"
  40 #include "northbridge/amd/amdk8/debug.c"
  41 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  42
  43 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  44 #include "cpu/x86/bist.h"
  45
  46 #include "northbridge/amd/amdk8/setup_resource_map.c"
  47
  48 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  49
  50 static void memreset_setup(void)
  51 {
  52 }
  53
  54 static void memreset(int controllers, const struct mem_controller *ctrl)
  55 {
  56 }
  57
  58 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  59 {
  60         /* nothing to do */
  61 }
  62
  63 static inline int spd_read_byte(unsigned device, unsigned address)
  64 {
  65         return smbus_read_byte(device, address);
  66 }
  67
  68 #define QRANK_DIMM_SUPPORT 1
  69
  70 #include "northbridge/amd/amdk8/raminit.c"
  71 #include "northbridge/amd/amdk8/coherent_ht.c"
  72 #include "sdram/generic_sdram.c"
  73
  74  /* tyan does not want the default */
  75 #include "resourcemap.c"
  76
  77 #if CONFIG_LOGICAL_CPUS==1
  78 #define SET_NB_CFG_54 1
  79 #endif
  80 #include "cpu/amd/dualcore/dualcore.c"
  81
  82 #define CK804_NUM 1
  83 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  84 //set GPIO to input mode
  85 #define CK804_MB_SETUP \
  86                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  87                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  88                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  89                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  90
  91 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  92
  93 #include "cpu/amd/car/copy_and_run.c"
  94
  95 #include "cpu/amd/car/post_cache_as_ram.c"
  96
  97 #include "cpu/amd/model_fxx/init_cpus.c"
  98
  99
 100 #if USE_FALLBACK_IMAGE == 1
 101
 102 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
 103 #include "northbridge/amd/amdk8/early_ht.c"
 104
 105 static void sio_setup(void)
 106 {
 107
 108         unsigned value;
 109         uint32_t dword;
 110         uint8_t byte;
 111
 112         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
 113         byte |= 0x20;
 114         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 115
 116         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 117         dword |= (1<<0);
 118         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 119
 120 }
 121 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 122 {
 123         unsigned last_boot_normal_x = last_boot_normal();
 124
 125         /* Is this a cpu only reset? or Is this a secondary cpu? */
 126         if ((cpu_init_detectedx) || (!boot_cpu())) {
 127                 if (last_boot_normal_x) {
 128                         goto normal_image;
 129                 } else {
 130                         goto fallback_image;
 131                 }
 132         }
 133
 134         /* Nothing special needs to be done to find bus 0 */
 135         /* Allow the HT devices to be found */
 136
 137         enumerate_ht_chain();
 138
 139         sio_setup();
 140
 141         /* Setup the ck804 */
 142         ck804_enable_rom();
 143
 144         /* Is this a deliberate reset by the bios */
 145 //        post_code(0x22);
 146         if (bios_reset_detected() && last_boot_normal_x) {
 147                 goto normal_image;
 148         }
 149         /* This is the primary cpu how should I boot? */
 150         else if (do_normal_boot()) {
 151                 goto normal_image;
 152         }
 153         else {
 154                 goto fallback_image;
 155         }
 156  normal_image:
 157 //        post_code(0x23);
 158         __asm__ volatile ("jmp __normal_image"
 159                 : /* outputs */
 160                 : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 161                 );
 162
 163  fallback_image:
 164 //        post_code(0x25);
 165         ;
 166 }
 167 #endif
 168
 169 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 170
 171 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 172 {
 173
 174 #if USE_FALLBACK_IMAGE == 1
 175         failover_process(bist, cpu_init_detectedx);
 176 #endif
 177         real_main(bist, cpu_init_detectedx);
 178
 179 }
 180
 181 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 182 {
 183
 184         static const uint16_t spd_addr [] = {
 185                         (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 186                         (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 187 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 188                         (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 189                         (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 190 #endif
 191         };
 192
 193         int needs_reset;
 194         unsigned bsp_apicid = 0;
 195
 196         struct mem_controller ctrl[8];
 197         unsigned nodes;
 198
 199         if (bist == 0) {
 200                 init_cpus(cpu_init_detectedx);
 201         }
 202
 203 //      post_code(0x32);
 204
 205         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 206         uart_init();
 207         console_init();
 208
 209         /* Halt if there was a built in self test failure */
 210         report_bist_failure(bist);
 211
 212         setup_s2892_resource_map();
 213 #if 0
 214         dump_pci_device(PCI_DEV(0, 0x18, 0));
 215         dump_pci_device(PCI_DEV(0, 0x19, 0));
 216 #endif
 217
 218         needs_reset = setup_coherent_ht_domain();
 219
 220         wait_all_core0_started();
 221 #if CONFIG_LOGICAL_CPUS==1
 222         // It is said that we should start core1 after all core0 launched
 223         start_other_cores();
 224         wait_all_other_cores_started(bsp_apicid);
 225 #endif
 226
 227         needs_reset |= ht_setup_chains_x();
 228
 229         needs_reset |= ck804_early_setup_x();
 230
 231         if (needs_reset) {
 232                 print_info("ht reset -\r\n");
 233                 soft_reset();
 234         }
 235
 236         allow_all_aps_stop(bsp_apicid);
 237
 238         nodes = get_nodes();
 239         //It's the time to set ctrl now;
 240         fill_mem_ctrl(nodes, ctrl, spd_addr);
 241
 242         enable_smbus();
 243 #if 0
 244         dump_spd_registers(&cpu[0]);
 245 #endif
 246 #if 0
 247         dump_smbus_registers();
 248 #endif
 249
 250         memreset_setup();
 251         sdram_initialize(nodes, ctrl);
 252
 253 #if 0
 254         print_pci_devices();
 255 #endif
 256
 257 #if 0
 258         dump_pci_devices();
 259 #endif
 260
 261         post_cache_as_ram();
 262 }