src/mainboard/tyan/s2892/cache_as_ram_auto.c

   1 #define ASSEMBLY 1
   2 #define __ROMCC__
   3
   4 #include <stdint.h>
   5 #include <string.h>
   6 #include <device/pci_def.h>
   7 #include <arch/io.h>
   8 #include <device/pnp_def.h>
   9 #include <arch/romcc_io.h>
  10 #include <cpu/x86/lapic.h>
  11 #include "option_table.h"
  12 #include "pc80/mc146818rtc_early.c"
  13 #include "pc80/serial.c"
  14 #include "arch/i386/lib/console.c"
  15 #include "ram/ramtest.c"
  16
  17 #include <cpu/amd/model_fxx_rev.h>
  18
  19 #include "northbridge/amd/amdk8/incoherent_ht.c"
  20 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  21 #include "northbridge/amd/amdk8/raminit.h"
  22 #include "cpu/amd/model_fxx/apic_timer.c"
  23 #include "lib/delay.c"
  24
  25 #include "cpu/x86/lapic/boot_cpu.c"
  26 #include "northbridge/amd/amdk8/reset_test.c"
  27 #include "northbridge/amd/amdk8/debug.c"
  28 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  29
  30 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  31 #include "cpu/x86/bist.h"
  32
  33 #include "northbridge/amd/amdk8/setup_resource_map.c"
  34
  35 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  36
  37 static void memreset_setup(void)
  38 {
  39 }
  40
  41 static void memreset(int controllers, const struct mem_controller *ctrl)
  42 {
  43 }
  44
  45 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  46 {
  47         /* nothing to do */
  48 }
  49
  50 static inline int spd_read_byte(unsigned device, unsigned address)
  51 {
  52         return smbus_read_byte(device, address);
  53 }
  54
  55 #define QRANK_DIMM_SUPPORT 1
  56
  57 #include "northbridge/amd/amdk8/raminit.c"
  58 #include "northbridge/amd/amdk8/coherent_ht.c"
  59 #include "sdram/generic_sdram.c"
  60
  61  /* tyan does not want the default */
  62 #include "resourcemap.c"
  63
  64 #if CONFIG_LOGICAL_CPUS==1
  65 #define SET_NB_CFG_54 1
  66 #endif
  67 #include "cpu/amd/dualcore/dualcore.c"
  68
  69 #define CK804_NUM 1
  70 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  71 //set GPIO to input mode
  72 #define CK804_MB_SETUP \
  73                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  74                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  75                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  76                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  77
  78 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  79
  80 #include "cpu/amd/car/copy_and_run.c"
  81
  82 #include "cpu/amd/car/post_cache_as_ram.c"
  83
  84 #include "cpu/amd/model_fxx/init_cpus.c"
  85
  86 #if USE_FALLBACK_IMAGE == 1
  87
  88 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  89 #include "northbridge/amd/amdk8/early_ht.c"
  90
  91 static void sio_setup(void)
  92 {
  93
  94         unsigned value;
  95         uint32_t dword;
  96         uint8_t byte;
  97
  98         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  99         byte |= 0x20;
 100         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
 101
 102         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
 103         dword |= (1<<0);
 104         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 105
 106 }
 107
 108 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 109 {
 110         unsigned last_boot_normal_x = last_boot_normal();
 111
 112         /* Is this a cpu only reset? or Is this a secondary cpu? */
 113         if ((cpu_init_detectedx) || (!boot_cpu())) {
 114         if (last_boot_normal_x) {
 115         goto normal_image;
 116         } else {
 117         goto fallback_image;
 118         }
 119         }
 120
 121         /* Nothing special needs to be done to find bus 0 */
 122         /* Allow the HT devices to be found */
 123
 124         enumerate_ht_chain();
 125
 126         sio_setup();
 127
 128         /* Setup the ck804 */
 129         ck804_enable_rom();
 130
 131         /* Is this a deliberate reset by the bios */
 132 //      post_code(0x22);
 133         if (bios_reset_detected() && last_boot_normal_x) {
 134         goto normal_image;
 135         }
 136         /* This is the primary cpu how should I boot? */
 137         else if (do_normal_boot()) {
 138         goto normal_image;
 139         }
 140         else {
 141         goto fallback_image;
 142         }
 143  normal_image:
 144 //      post_code(0x23);
 145         __asm__ volatile ("jmp __normal_image"
 146         : /* outputs */
 147         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 148         );
 149
 150  fallback_image:
 151 //      post_code(0x25);
 152         ;
 153 }
 154 #endif
 155
 156 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 157
 158 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 159 {
 160
 161 #if USE_FALLBACK_IMAGE == 1
 162                 failover_process(bist, cpu_init_detectedx);
 163 #endif
 164         real_main(bist, cpu_init_detectedx);
 165
 166 }
 167
 168 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 169 {
 170         static const uint16_t spd_addr [] = {
 171                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 172                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 173 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 174                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 175                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 176 #endif
 177         };
 178
 179         int needs_reset;
 180         unsigned bsp_apicid = 0;
 181
 182         struct mem_controller ctrl[8];
 183         unsigned nodes;
 184
 185         if (bist == 0) {
 186                 init_cpus(cpu_init_detectedx);
 187         }
 188
 189 //      post_code(0x32);
 190
 191         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 192         uart_init();
 193         console_init();
 194
 195         /* Halt if there was a built in self test failure */
 196         report_bist_failure(bist);
 197
 198         setup_s2892_resource_map();
 199 #if 0
 200         dump_pci_device(PCI_DEV(0, 0x18, 0));
 201         dump_pci_device(PCI_DEV(0, 0x19, 0));
 202 #endif
 203
 204         needs_reset = setup_coherent_ht_domain();
 205
 206         wait_all_core0_started();
 207 #if CONFIG_LOGICAL_CPUS==1
 208         // It is said that we should start core1 after all core0 launched
 209         start_other_cores();
 210         wait_all_other_cores_started(bsp_apicid);
 211 #endif
 212
 213         needs_reset |= ht_setup_chains_x();
 214
 215         needs_reset |= ck804_early_setup_x();
 216
 217         if (needs_reset) {
 218                 print_info("ht reset -\r\n");
 219                 soft_reset();
 220         }
 221
 222         allow_all_aps_stop(bsp_apicid);
 223
 224         nodes = get_nodes();
 225         //It's the time to set ctrl now;
 226         fill_mem_ctrl(nodes, ctrl, spd_addr);
 227
 228         enable_smbus();
 229 #if 0
 230         dump_spd_registers(&cpu[0]);
 231 #endif
 232 #if 0
 233         dump_smbus_registers();
 234 #endif
 235
 236         memreset_setup();
 237         sdram_initialize(nodes, ctrl);
 238
 239 #if 0
 240         print_pci_devices();
 241 #endif
 242
 243 #if 0
 244         dump_pci_devices();
 245 #endif
 246
 247         post_cache_as_ram();
 248 }