src/mainboard/tyan/s2892/auto.c

   1 #define ASSEMBLY 1
   2
   3 #include <stdint.h>
   4 #include <device/pci_def.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_def.h>
   7 #include <arch/romcc_io.h>
   8 #include <cpu/x86/lapic.h>
   9 #include "option_table.h"
  10 #include "pc80/mc146818rtc_early.c"
  11 #include "pc80/serial.c"
  12 #include "arch/i386/lib/console.c"
  13 #include "ram/ramtest.c"
  14
  15 #include "northbridge/amd/amdk8/cpu_rev.c"
  16 #define K8_HT_FREQ_1G_SUPPORT 1
  17 #include "northbridge/amd/amdk8/incoherent_ht.c"
  18 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  19 #include "northbridge/amd/amdk8/raminit.h"
  20 #include "cpu/amd/model_fxx/apic_timer.c"
  21 #include "lib/delay.c"
  22 #include "cpu/x86/lapic/boot_cpu.c"
  23 #include "northbridge/amd/amdk8/reset_test.c"
  24 #include "northbridge/amd/amdk8/debug.c"
  25 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  26
  27 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  28 #include "cpu/x86/bist.h"
  29 #include "cpu/amd/dualcore/dualcore.c"
  30
  31 #include "northbridge/amd/amdk8/setup_resource_map.c"
  32
  33 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  34
  35 static void hard_reset(void)
  36 {
  37         set_bios_reset();
  38
  39         /* full reset */
  40         outb(0x0a, 0x0cf9);
  41         outb(0x0e, 0x0cf9);
  42 }
  43
  44 static void soft_reset(void)
  45 {
  46         set_bios_reset();
  47 #if 1
  48         /* link reset */
  49         outb(0x02, 0x0cf9);
  50         outb(0x06, 0x0cf9);
  51 #endif
  52 }
  53
  54 static void memreset_setup(void)
  55 {
  56 }
  57
  58 static void memreset(int controllers, const struct mem_controller *ctrl)
  59 {
  60 }
  61
  62 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  63 {
  64         /* nothing to do */
  65 }
  66
  67 static inline int spd_read_byte(unsigned device, unsigned address)
  68 {
  69         return smbus_read_byte(device, address);
  70 }
  71
  72 #define K8_4RANK_DIMM_SUPPORT 1
  73 #include "northbridge/amd/amdk8/raminit.c"
  74 #include "northbridge/amd/amdk8/coherent_ht.c"
  75 #include "sdram/generic_sdram.c"
  76
  77  /* tyan does not want the default */
  78 #include "resourcemap.c"
  79
  80 #define FIRST_CPU  1
  81 #define SECOND_CPU 1
  82 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
  83
  84 #define CK804_NUM 1
  85 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  86 //set GPIO to input mode
  87 #define CK804_MB_SETUP \
  88                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
  89                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+44, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P5,GPIO45, PCIXA_PRSNT1_L*/ \
  90                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+16, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* K4,GPIO17, PCIXB_PRSNT1_L*/ \
  91                 RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
  92
  93 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  94
  95
  96 static void main(unsigned long bist)
  97 {
  98         static const struct mem_controller cpu[] = {
  99 #if FIRST_CPU
 100                 {
 101                         .node_id = 0,
 102                         .f0 = PCI_DEV(0, 0x18, 0),
 103                         .f1 = PCI_DEV(0, 0x18, 1),
 104                         .f2 = PCI_DEV(0, 0x18, 2),
 105                         .f3 = PCI_DEV(0, 0x18, 3),
 106                         .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
 107                         .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
 108                 },
 109 #endif
 110 #if SECOND_CPU
 111                 {
 112                         .node_id = 1,
 113                         .f0 = PCI_DEV(0, 0x19, 0),
 114                         .f1 = PCI_DEV(0, 0x19, 1),
 115                         .f2 = PCI_DEV(0, 0x19, 2),
 116                         .f3 = PCI_DEV(0, 0x19, 3),
 117                         .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
 118                         .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
 119                 },
 120 #endif
 121         };
 122
 123         int needs_reset;
 124
 125         if (bist == 0) {
 126                 k8_init_and_stop_secondaries();
 127         }
 128
 129
 130         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
 131         uart_init();
 132         console_init();
 133
 134         /* Halt if there was a built in self test failure */
 135 //      report_bist_failure(bist);
 136
 137         setup_s2892_resource_map();
 138
 139         needs_reset = setup_coherent_ht_domain();
 140
 141         needs_reset |= ht_setup_chains_x();
 142
 143         needs_reset |= ck804_early_setup_x();
 144
 145         if (needs_reset) {
 146                 print_info("ht reset -\r\n");
 147                 soft_reset();
 148         }
 149
 150         enable_smbus();
 151
 152         memreset_setup();
 153         sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 154
 155 }