4 uses USE_FALLBACK_IMAGE
5 uses HAVE_FALLBACK_BOOT
10 uses CONFIG_MAX_PHYSICAL_CPUS
11 uses CONFIG_LOGICAL_CPUS
19 uses ROM_SECTION_OFFSET
20 uses CONFIG_ROM_PAYLOAD
21 uses CONFIG_ROM_PAYLOAD_START
22 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
23 uses CONFIG_PRECOMPRESSED_PAYLOAD
31 uses LB_CKS_RANGE_START
41 uses MAINBOARD_PART_NUMBER
43 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
44 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
45 uses COREBOOT_EXTRA_VERSION
55 uses DEFAULT_CONSOLE_LOGLEVEL
56 uses MAXIMUM_CONSOLE_LOGLEVEL
57 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
58 uses CONFIG_CONSOLE_SERIAL8250
59 uses CONFIG_CONSOLE_BTEXT
62 uses CONFIG_CONSOLE_VGA
63 uses CONFIG_VGA_ROM_RUN
64 uses CONFIG_PCI_ROM_RUN
65 uses HW_MEM_HOLE_SIZEK
71 uses CONFIG_USE_PRINTK_IN_CAR
73 uses HT_CHAIN_UNITID_BASE
74 uses HT_CHAIN_END_UNITID_BASE
75 uses SB_HT_CHAIN_ON_BUS0
76 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
78 uses CONFIG_LB_MEM_TOPK
80 ## ROM_SIZE is the size of boot ROM that this board will use.
81 default ROM_SIZE=1024*1024
84 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
86 #default FALLBACK_SIZE=131072
88 default FALLBACK_SIZE=0x40000
95 ## Build code for the fallback boot
97 default HAVE_FALLBACK_BOOT=1
100 ## Build code to reset the motherboard from coreboot
102 default HAVE_HARD_RESET=1
107 default HAVE_SMI_HANDLER=0
110 ## Build code to export a programmable irq routing table
112 default HAVE_PIRQ_TABLE=1
113 default IRQ_SLOT_COUNT=11
116 ## Build code to export an x86 MP table
117 ## Useful for specifying IRQ routing values
119 default HAVE_MP_TABLE=1
122 ## Build code to provide ACPI support
124 default HAVE_ACPI_TABLES=1
125 default HAVE_LOW_TABLES=1
126 default HAVE_HIGH_TABLES=1
127 default CONFIG_MULTIBOOT=0
130 ## Build code to export a CMOS option table
132 default HAVE_OPTION_TABLE=1
135 ## Move the default coreboot cmos range off of AMD RTC registers
137 default LB_CKS_RANGE_START=49
138 default LB_CKS_RANGE_END=122
139 default LB_CKS_LOC=123
142 default CONFIG_CONSOLE_VGA=1
143 default CONFIG_PCI_ROM_RUN=1
144 default CONFIG_VGA_ROM_RUN=1
147 ## Build code for SMP support
148 ## Only worry about 2 micro processors
151 default CONFIG_MAX_CPUS=4
152 default CONFIG_MAX_PHYSICAL_CPUS=2
153 default CONFIG_LOGICAL_CPUS=1
156 default HW_MEM_HOLE_SIZEK=0x100000
158 ##HT Unit ID offset, default is 1, the typical one
159 default HT_CHAIN_UNITID_BASE=0x0
161 ##real SB Unit ID, default is 0x20, mean dont touch it at last
162 #default HT_CHAIN_END_UNITID_BASE=0x0
164 #make the SB HT chain on bus 0, default is not (0)
165 default SB_HT_CHAIN_ON_BUS0=2
167 ##only offset for SB chain?, default is yes(1)
168 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
171 #default CONFIG_CONSOLE_BTEXT=1
174 default CONFIG_CONSOLE_VGA=1
175 default CONFIG_PCI_ROM_RUN=1
178 ## enable CACHE_AS_RAM specifics
180 default USE_DCACHE_RAM=1
181 default DCACHE_RAM_BASE=0xcf000
182 default DCACHE_RAM_SIZE=0x1000
183 default CONFIG_USE_INIT=0
187 ## Build code to setup a generic IOAPIC
189 default CONFIG_IOAPIC=1
192 ## Clean up the motherboard id strings
194 default MAINBOARD_PART_NUMBER="s2892"
195 default MAINBOARD_VENDOR="Tyan"
196 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
197 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892
200 ### coreboot layout values
203 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
204 default ROM_IMAGE_SIZE = 65536
207 ## Use a small 8K stack
209 default STACK_SIZE=0x2000
212 ## Use a small 16K heap
214 default HEAP_SIZE=0x4000
217 ## Only use the option table in a normal image
219 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
222 ## Coreboot C code runs at this location in RAM
224 default _RAMBASE=0x00004000
227 ## Load the payload from the ROM
229 default CONFIG_ROM_PAYLOAD = 1
232 ### Defaults of options that you may want to override in the target config file
236 ## The default compiler
238 default CC="$(CROSS_COMPILE)gcc -m32"
242 ## Disable the gdb stub by default
244 default CONFIG_GDB_STUB=0
246 default CONFIG_USE_PRINTK_IN_CAR=1
249 ## The Serial Console
252 # To Enable the Serial Console
253 default CONFIG_CONSOLE_SERIAL8250=1
255 ## Select the serial console baud rate
256 default TTYS0_BAUD=115200
257 #default TTYS0_BAUD=57600
258 #default TTYS0_BAUD=38400
259 #default TTYS0_BAUD=19200
260 #default TTYS0_BAUD=9600
261 #default TTYS0_BAUD=4800
262 #default TTYS0_BAUD=2400
263 #default TTYS0_BAUD=1200
265 # Select the serial console base port
266 default TTYS0_BASE=0x3f8
268 # Select the serial protocol
269 # This defaults to 8 data bits, 1 stop bit, and no parity
270 default TTYS0_LCS=0x3
273 ### Select the coreboot loglevel
275 ## EMERG 1 system is unusable
276 ## ALERT 2 action must be taken immediately
277 ## CRIT 3 critical conditions
278 ## ERR 4 error conditions
279 ## WARNING 5 warning conditions
280 ## NOTICE 6 normal but significant condition
281 ## INFO 7 informational
282 ## DEBUG 8 debug-level messages
283 ## SPEW 9 Way too many details
285 ## Request this level of debugging output
286 default DEFAULT_CONSOLE_LOGLEVEL=8
287 ## At a maximum only compile in this level of debugging
288 default MAXIMUM_CONSOLE_LOGLEVEL=8
291 ## Select power on after power fail setting
292 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
299 default CONFIG_CBFS=0