3 uses USE_FALLBACK_IMAGE
4 uses HAVE_FALLBACK_BOOT
9 uses CONFIG_MAX_PHYSICAL_CPUS
10 uses CONFIG_LOGICAL_CPUS
18 uses ROM_SECTION_OFFSET
19 uses CONFIG_ROM_PAYLOAD
20 uses CONFIG_ROM_PAYLOAD_START
21 uses CONFIG_COMPRESSED_PAYLOAD_LZMA
22 uses CONFIG_PRECOMPRESSED_PAYLOAD
30 uses LB_CKS_RANGE_START
34 uses HAVE_MAINBOARD_RESOURCES
40 uses MAINBOARD_PART_NUMBER
42 uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
43 uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
44 uses COREBOOT_EXTRA_VERSION
54 uses DEFAULT_CONSOLE_LOGLEVEL
55 uses MAXIMUM_CONSOLE_LOGLEVEL
56 uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
57 uses CONFIG_CONSOLE_SERIAL8250
58 uses CONFIG_CONSOLE_BTEXT
62 uses CONFIG_CONSOLE_VGA
63 uses CONFIG_VGA_ROM_RUN
64 uses CONFIG_PCI_ROM_RUN
65 uses HW_MEM_HOLE_SIZEK
71 uses CONFIG_USE_PRINTK_IN_CAR
73 uses HT_CHAIN_UNITID_BASE
74 uses HT_CHAIN_END_UNITID_BASE
75 uses SB_HT_CHAIN_ON_BUS0
76 uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
78 uses CONFIG_LB_MEM_TOPK
80 ## ROM_SIZE is the size of boot ROM that this board will use.
81 default ROM_SIZE=1024*1024
84 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
86 #default FALLBACK_SIZE=131072
88 default FALLBACK_SIZE=0x40000
95 ## Build code for the fallback boot
97 default HAVE_FALLBACK_BOOT=1
100 ## Build code to reset the motherboard from coreboot
102 default HAVE_HARD_RESET=1
107 default HAVE_SMI_HANDLER=0
110 ## Build code to export a programmable irq routing table
112 default HAVE_PIRQ_TABLE=1
113 default IRQ_SLOT_COUNT=11
116 ## Build code to export an x86 MP table
117 ## Useful for specifying IRQ routing values
119 default HAVE_MP_TABLE=1
122 ## Build code to provide ACPI support
124 default HAVE_ACPI_TABLES=1
125 default HAVE_LOW_TABLES=1
126 default HAVE_MAINBOARD_RESOURCES=1
127 default HAVE_HIGH_TABLES=0
128 default CONFIG_MULTIBOOT=0
131 ## Build code to export a CMOS option table
133 default HAVE_OPTION_TABLE=1
136 ## Move the default coreboot cmos range off of AMD RTC registers
138 default LB_CKS_RANGE_START=49
139 default LB_CKS_RANGE_END=122
140 default LB_CKS_LOC=123
143 default CONFIG_CONSOLE_VGA=1
144 default CONFIG_PCI_ROM_RUN=1
145 default CONFIG_VGA_ROM_RUN=1
148 ## Build code for SMP support
149 ## Only worry about 2 micro processors
152 default CONFIG_MAX_CPUS=4
153 default CONFIG_MAX_PHYSICAL_CPUS=2
154 default CONFIG_LOGICAL_CPUS=1
157 default HW_MEM_HOLE_SIZEK=0x100000
159 ##HT Unit ID offset, default is 1, the typical one
160 default HT_CHAIN_UNITID_BASE=0x0
162 ##real SB Unit ID, default is 0x20, mean dont touch it at last
163 #default HT_CHAIN_END_UNITID_BASE=0x0
165 #make the SB HT chain on bus 0, default is not (0)
166 default SB_HT_CHAIN_ON_BUS0=2
168 ##only offset for SB chain?, default is yes(1)
169 default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
172 #default CONFIG_CONSOLE_BTEXT=1
175 default CONFIG_CONSOLE_VGA=1
176 default CONFIG_PCI_ROM_RUN=1
179 ## enable CACHE_AS_RAM specifics
181 default USE_DCACHE_RAM=1
182 default DCACHE_RAM_BASE=0xcf000
183 default DCACHE_RAM_SIZE=0x1000
184 default CONFIG_USE_INIT=0
188 ## Build code to setup a generic IOAPIC
190 default CONFIG_IOAPIC=1
193 ## Clean up the motherboard id strings
195 default MAINBOARD_PART_NUMBER="s2892"
196 default MAINBOARD_VENDOR="Tyan"
197 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
198 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2892
201 ### coreboot layout values
204 ## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
205 default ROM_IMAGE_SIZE = 65536
208 ## Use a small 8K stack
210 default STACK_SIZE=0x2000
213 ## Use a small 16K heap
215 default HEAP_SIZE=0x4000
218 ## Only use the option table in a normal image
220 default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
223 ## Coreboot C code runs at this location in RAM
225 default _RAMBASE=0x00004000
228 ## Load the payload from the ROM
230 default CONFIG_ROM_PAYLOAD = 1
233 ### Defaults of options that you may want to override in the target config file
237 ## The default compiler
239 default CC="$(CROSS_COMPILE)gcc -m32"
243 ## Disable the gdb stub by default
245 default CONFIG_GDB_STUB=0
247 default CONFIG_USE_PRINTK_IN_CAR=1
250 ## The Serial Console
253 # To Enable the Serial Console
254 default CONFIG_CONSOLE_SERIAL8250=1
256 ## Select the serial console baud rate
257 default TTYS0_BAUD=115200
258 #default TTYS0_BAUD=57600
259 #default TTYS0_BAUD=38400
260 #default TTYS0_BAUD=19200
261 #default TTYS0_BAUD=9600
262 #default TTYS0_BAUD=4800
263 #default TTYS0_BAUD=2400
264 #default TTYS0_BAUD=1200
266 # Select the serial console base port
267 default TTYS0_BASE=0x3f8
269 # Select the serial protocol
270 # This defaults to 8 data bits, 1 stop bit, and no parity
271 default TTYS0_LCS=0x3
274 ### Select the coreboot loglevel
276 ## EMERG 1 system is unusable
277 ## ALERT 2 action must be taken immediately
278 ## CRIT 3 critical conditions
279 ## ERR 4 error conditions
280 ## WARNING 5 warning conditions
281 ## NOTICE 6 normal but significant condition
282 ## INFO 7 informational
283 ## DEBUG 8 debug-level messages
284 ## SPEW 9 Way too many details
286 ## Request this level of debugging output
287 default DEFAULT_CONSOLE_LOGLEVEL=8
288 ## At a maximum only compile in this level of debugging
289 default MAXIMUM_CONSOLE_LOGLEVEL=8
292 ## Select power on after power fail setting
293 default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"