2 ## Compute the location and size of where this firmware image
3 ## (coreboot plus bootloader) will live in the boot rom chip.
6 default ROM_SECTION_SIZE = FALLBACK_SIZE
7 default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
9 default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
10 default ROM_SECTION_OFFSET = 0
14 ## Compute the start location and size size of
15 ## The coreboot bootloader.
17 default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
18 default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
19 default CONFIG_ROM_PAYLOAD = 1
22 ## Compute where this copy of coreboot will start in the boot rom
24 default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE )
27 ## Compute a range of ROM that can cached to speed up coreboot,
30 ## XIP_ROM_SIZE must be a power of 2.
31 ## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
33 default XIP_ROM_SIZE=65536
34 default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
40 ## Build the objects we have code for in this directory.
45 #dir /drivers/ati/ragexl
47 #needed by irq_tables and mptable and acpi_tables
50 if HAVE_MP_TABLE object mptable.o end
51 if HAVE_PIRQ_TABLE object irq_tables.o end
58 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
59 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
63 depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
64 action "$(CC) $(DISTRO_CFLAGS) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
65 action "perl -e 's/.rodata/.rom.data/g' -pi $@"
66 action "perl -e 's/.text/.section .rom.text/g' -pi $@"
75 depends "$(MAINBOARD)/failover.c ../romcc"
76 action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
79 makerule ./failover.inc
80 depends "$(MAINBOARD)/failover.c ../romcc"
81 action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
85 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
86 action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
90 depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
91 action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
97 ## Build our 16 bit and 32 bit coreboot entry code
100 mainboardinit cpu/x86/16bit/entry16.inc
101 ldscript /cpu/x86/16bit/entry16.lds
104 mainboardinit cpu/x86/32bit/entry32.inc
108 ldscript /cpu/x86/32bit/entry32.lds
112 ldscript /cpu/amd/car/cache_as_ram.lds
117 ## Build our reset vector (This is where coreboot is entered)
119 if USE_FALLBACK_IMAGE
120 mainboardinit cpu/x86/16bit/reset16.inc
121 ldscript /cpu/x86/16bit/reset16.lds
123 mainboardinit cpu/x86/32bit/reset32.inc
124 ldscript /cpu/x86/32bit/reset32.lds
129 ### Should this be in the northbridge code?
130 mainboardinit arch/i386/lib/cpu_reset.inc
134 ## Include an id string (For safe flashing)
136 mainboardinit southbridge/nvidia/ck804/id.inc
137 ldscript /southbridge/nvidia/ck804/id.lds
140 ## ROMSTRAP table for CK804
142 if USE_FALLBACK_IMAGE
143 mainboardinit southbridge/nvidia/ck804/romstrap.inc
144 ldscript /southbridge/nvidia/ck804/romstrap.lds
149 ## Setup Cache-As-Ram
151 mainboardinit cpu/amd/car/cache_as_ram.inc
155 ### This is the early phase of coreboot startup
156 ### Things are delicate and we test to see if we should
157 ### failover to another image.
159 if USE_FALLBACK_IMAGE
161 ldscript /arch/i386/lib/failover.lds
163 ldscript /arch/i386/lib/failover.lds
164 mainboardinit ./failover.inc
169 ### O.k. We aren't just an intermediary anymore!
180 mainboardinit ./auto.inc
185 mainboardinit cpu/x86/fpu/enable_fpu.inc
186 mainboardinit cpu/x86/mmx/enable_mmx.inc
187 mainboardinit cpu/x86/sse/enable_sse.inc
188 mainboardinit ./auto.inc
189 mainboardinit cpu/x86/sse/disable_sse.inc
190 mainboardinit cpu/x86/mmx/disable_mmx.inc
195 ## Include the secondary Configuration files
201 # sample config for tyan/s2892
202 chip northbridge/amd/amdk8/root_complex
203 device apic_cluster 0 on
204 chip cpu/amd/socket_940
208 device pci_domain 0 on
209 chip northbridge/amd/amdk8 #mc0
210 device pci 18.0 on # northbridge
211 # devices on link 0, link 0 == LDT 0
212 chip southbridge/nvidia/ck804
213 device pci 0.0 on end # HT
214 device pci 1.0 on # LPC
215 chip superio/winbond/w83627hf
216 device pnp 2e.0 on # Floppy
221 device pnp 2e.1 off # Parallel Port
225 device pnp 2e.2 on # Com1
229 device pnp 2e.3 off # Com2
233 device pnp 2e.5 on # Keyboard
239 device pnp 2e.6 off # CIR
242 device pnp 2e.7 off # GAME_MIDI_GIPO1
247 device pnp 2e.8 off end # GPIO2
248 device pnp 2e.9 off end # GPIO3
249 device pnp 2e.a off end # ACPI
250 device pnp 2e.b on # HW Monitor
256 device pci 1.1 on # SM 0
257 chip drivers/generic/generic #dimm 0-0-0
260 chip drivers/generic/generic #dimm 0-0-1
263 chip drivers/generic/generic #dimm 0-1-0
266 chip drivers/generic/generic #dimm 0-1-1
269 chip drivers/generic/generic #dimm 1-0-0
272 chip drivers/generic/generic #dimm 1-0-1
275 chip drivers/generic/generic #dimm 1-1-0
278 chip drivers/generic/generic #dimm 1-1-1
282 device pci 1.1 on # SM 1
283 chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
286 chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
289 chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
292 chip drivers/generic/generic # Winbond HWM 0x92
295 chip drivers/generic/generic # Winbond HWM 0x94
299 device pci 2.0 on end # USB 1.1
300 device pci 2.1 on end # USB 2
301 device pci 4.0 off end # ACI
302 device pci 4.1 off end # MCI
303 device pci 6.0 on end # IDE
304 device pci 7.0 on end # SATA 1
305 device pci 8.0 on end # SATA 0
306 device pci 9.0 on # PCI
307 # chip drivers/ati/ragexl
308 chip drivers/pci/onboard
309 device pci 6.0 on end
310 register "rom_address" = "0xfff80000"
312 chip drivers/pci/onboard
313 device pci 8.0 on end
316 device pci a.0 off end # NIC
317 device pci b.0 off end # PCI E 3
318 device pci c.0 off end # PCI E 2
319 device pci d.0 on end # PCI E 1
320 device pci e.0 on end # PCI E 0
321 register "ide0_enable" = "1"
322 register "ide1_enable" = "1"
323 register "sata0_enable" = "1"
324 register "sata1_enable" = "1"
326 end # device pci 18.0
327 device pci 18.0 on end # Link 1
329 # devices on link 2, link 2 == LDT 2
330 chip southbridge/amd/amd8131
331 # the on/off keyword is mandatory
332 device pci 0.0 on end
333 device pci 0.1 on end
335 chip drivers/pci/onboard
336 device pci 9.0 on end # broadcom 5704
337 device pci 9.1 on end
340 device pci 1.1 on end
342 end # device pci 18.0
343 device pci 18.1 on end
344 device pci 18.2 on end
345 device pci 18.3 on end
350 # chip drivers/generic/debug
351 # device pnp 0.0 off end
352 # device pnp 0.1 off end
353 # device pnp 0.2 off end
354 # device pnp 0.3 off end
355 # device pnp 0.4 off end
356 # device pnp 0.5 on end