1 ## CONFIG_XIP_ROM_SIZE must be a power of 2.
2 default CONFIG_XIP_ROM_SIZE = 64 * 1024
3 include /config/nofailovercalculation.lb
4 default CONFIG_ROM_PAYLOAD = 1
10 ## Build the objects we have code for in this directory.
15 #dir /drivers/ati/ragexl
17 #needed by irq_tables and mptable and acpi_tables
20 if CONFIG_HAVE_MP_TABLE object mptable.o end
21 if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
24 if CONFIG_HAVE_ACPI_TABLES
27 depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
28 action "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
29 action "mv dsdt.hex dsdt.c"
32 #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
33 #./fadt.o is moved to southbridge/nvidia/ck804/Config.lb
38 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
39 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
43 depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
44 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
45 action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
46 action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
51 ## Build our 16 bit and 32 bit coreboot entry code
53 if CONFIG_USE_FALLBACK_IMAGE
54 mainboardinit cpu/x86/16bit/entry16.inc
55 ldscript /cpu/x86/16bit/entry16.lds
58 mainboardinit cpu/x86/32bit/entry32.inc
61 ldscript /cpu/x86/32bit/entry32.lds
65 ldscript /cpu/amd/car/cache_as_ram.lds
69 ## Build our reset vector (This is where coreboot is entered)
71 if CONFIG_USE_FALLBACK_IMAGE
72 mainboardinit cpu/x86/16bit/reset16.inc
73 ldscript /cpu/x86/16bit/reset16.lds
75 mainboardinit cpu/x86/32bit/reset32.inc
76 ldscript /cpu/x86/32bit/reset32.lds
80 ## Include an id string (For safe flashing)
82 mainboardinit southbridge/nvidia/ck804/id.inc
83 ldscript /southbridge/nvidia/ck804/id.lds
86 ## ROMSTRAP table for CK804
88 if CONFIG_USE_FALLBACK_IMAGE
89 mainboardinit southbridge/nvidia/ck804/romstrap.inc
90 ldscript /southbridge/nvidia/ck804/romstrap.lds
96 mainboardinit cpu/amd/car/cache_as_ram.inc
99 ### This is the early phase of coreboot startup
100 ### Things are delicate and we test to see if we should
101 ### failover to another image.
103 if CONFIG_USE_FALLBACK_IMAGE
104 ldscript /arch/i386/lib/failover.lds
108 ### O.k. We aren't just an intermediary anymore!
117 mainboardinit ./auto.inc
121 ## Include the secondary Configuration files
125 # sample config for tyan/s2892
126 chip northbridge/amd/amdk8/root_complex
127 device apic_cluster 0 on
128 chip cpu/amd/socket_940
132 device pci_domain 0 on
133 chip northbridge/amd/amdk8 #mc0
134 device pci 18.0 on # northbridge
135 # devices on link 0, link 0 == LDT 0
136 chip southbridge/nvidia/ck804
137 device pci 0.0 on end # HT
138 device pci 1.0 on # LPC
139 chip superio/winbond/w83627hf
140 device pnp 2e.0 on # Floppy
145 device pnp 2e.1 on # Parallel Port
150 device pnp 2e.2 on # Com1
154 device pnp 2e.3 off # Com2
158 device pnp 2e.5 on # Keyboard
164 device pnp 2e.6 off # CIR
167 device pnp 2e.7 off # GAME_MIDI_GIPO1
172 device pnp 2e.8 off end # GPIO2
173 device pnp 2e.9 off end # GPIO3
174 device pnp 2e.a off end # ACPI
175 device pnp 2e.b on # HW Monitor
181 device pci 1.1 on # SM 0
182 chip drivers/generic/generic #dimm 0-0-0
185 chip drivers/generic/generic #dimm 0-0-1
188 chip drivers/generic/generic #dimm 0-1-0
191 chip drivers/generic/generic #dimm 0-1-1
194 chip drivers/generic/generic #dimm 1-0-0
197 chip drivers/generic/generic #dimm 1-0-1
200 chip drivers/generic/generic #dimm 1-1-0
203 chip drivers/generic/generic #dimm 1-1-1
207 device pci 1.1 on # SM 1
208 chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4
211 chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5
214 chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN
217 chip drivers/generic/generic # Winbond HWM 0x92
220 chip drivers/generic/generic # Winbond HWM 0x94
224 device pci 2.0 on end # USB 1.1
225 device pci 2.1 on end # USB 2
226 device pci 4.0 off end # ACI
227 device pci 4.1 off end # MCI
228 device pci 6.0 on end # IDE
229 device pci 7.0 on end # SATA 1
230 device pci 8.0 on end # SATA 0
231 device pci 9.0 on # PCI
232 # chip drivers/ati/ragexl
233 chip drivers/pci/onboard
234 device pci 6.0 on end
235 register "rom_address" = "0xfff80000"
237 chip drivers/pci/onboard
238 device pci 8.0 on end
241 device pci a.0 off end # NIC
242 device pci b.0 off end # PCI E 3
243 device pci c.0 off end # PCI E 2
244 device pci d.0 on end # PCI E 1
245 device pci e.0 on end # PCI E 0
246 register "ide0_enable" = "1"
247 register "ide1_enable" = "1"
248 register "sata0_enable" = "1"
249 register "sata1_enable" = "1"
251 end # device pci 18.0
252 device pci 18.0 on end # Link 1
254 # devices on link 2, link 2 == LDT 2
255 chip southbridge/amd/amd8131
256 # the on/off keyword is mandatory
257 device pci 0.0 on end
258 device pci 0.1 on end
260 chip drivers/pci/onboard
261 device pci 9.0 on end # broadcom 5704
262 device pci 9.1 on end
265 device pci 1.1 on end
267 end # device pci 18.0
268 device pci 18.1 on end
269 device pci 18.2 on end
270 device pci 18.3 on end
275 # chip drivers/generic/debug
276 # device pnp 0.0 off end
277 # device pnp 0.1 off end
278 # device pnp 0.2 off end
279 # device pnp 0.3 off end
280 # device pnp 0.4 off end
281 # device pnp 0.5 on end