2 #define QRANK_DIMM_SUPPORT 1
4 #if CONFIG_LOGICAL_CPUS==1
5 #define SET_NB_CFG_54 1
10 #include <device/pci_def.h>
12 #include <device/pnp_def.h>
13 #include <arch/romcc_io.h>
14 #include <cpu/x86/lapic.h>
15 #include "option_table.h"
16 #include "pc80/mc146818rtc_early.c"
17 #include "pc80/serial.c"
18 #include "arch/i386/lib/console.c"
19 #include "lib/ramtest.c"
21 #include <cpu/amd/model_fxx_rev.h>
23 #include "northbridge/amd/amdk8/incoherent_ht.c"
24 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
25 #include "northbridge/amd/amdk8/raminit.h"
26 #include "cpu/amd/model_fxx/apic_timer.c"
27 #include "lib/delay.c"
28 #include "cpu/x86/lapic/boot_cpu.c"
29 #include "northbridge/amd/amdk8/reset_test.c"
30 #include "northbridge/amd/amdk8/debug.c"
31 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
33 #include "cpu/amd/mtrr/amd_earlymtrr.c"
34 #include "cpu/x86/bist.h"
36 #include "northbridge/amd/amdk8/setup_resource_map.c"
38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
40 static void memreset_setup(void)
44 static void memreset(int controllers, const struct mem_controller *ctrl)
48 static inline void activate_spd_rom(const struct mem_controller *ctrl)
53 static inline int spd_read_byte(unsigned device, unsigned address)
55 return smbus_read_byte(device, address);
58 #include "northbridge/amd/amdk8/raminit.c"
59 #include "northbridge/amd/amdk8/coherent_ht.c"
60 #include "lib/generic_sdram.c"
62 /* tyan does not want the default */
63 #include "resourcemap.c"
65 #include "cpu/amd/dualcore/dualcore.c"
68 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
69 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
71 #include "cpu/amd/car/copy_and_run.c"
73 #include "cpu/amd/car/post_cache_as_ram.c"
75 #include "cpu/amd/model_fxx/init_cpus.c"
77 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
78 #include "northbridge/amd/amdk8/early_ht.c"
80 static void sio_setup(void)
88 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
90 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
92 /* LPC Positive Decode 0 */
93 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
94 /* Serial 0, Serial 1 */
95 dword |= (1<<0) | (1<<1);
96 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
99 /* s2891 has onboard LPC port 80 */
100 /*Hope I can enable port 80 here
101 It will decode port 80 to LPC, If you are using PCI post code you can not do this */
102 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
104 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
110 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
112 static const uint16_t spd_addr [] = {
113 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
114 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
115 #if CONFIG_MAX_PHYSICAL_CPUS > 1
116 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
117 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
122 unsigned bsp_apicid = 0;
124 struct mem_controller ctrl[8];
127 if (!cpu_init_detectedx && boot_cpu()) {
128 /* Nothing special needs to be done to find bus 0 */
129 /* Allow the HT devices to be found */
131 enumerate_ht_chain();
135 /* Setup the ck804 */
140 bsp_apicid = init_cpus(cpu_init_detectedx);
145 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
149 /* Halt if there was a built in self test failure */
150 report_bist_failure(bist);
152 setup_s2891_resource_map();
154 dump_pci_device(PCI_DEV(0, 0x18, 0));
155 dump_pci_device(PCI_DEV(0, 0x19, 0));
158 needs_reset = setup_coherent_ht_domain();
160 wait_all_core0_started();
161 #if CONFIG_LOGICAL_CPUS==1
162 // It is said that we should start core1 after all core0 launched
164 wait_all_other_cores_started(bsp_apicid);
167 needs_reset |= ht_setup_chains_x();
169 needs_reset |= ck804_early_setup_x();
172 printk(BIOS_INFO, "ht reset -\r\n");
176 allow_all_aps_stop(bsp_apicid);
179 //It's the time to set ctrl now;
180 fill_mem_ctrl(nodes, ctrl, spd_addr);
184 dump_spd_registers(&cpu[0]);
187 dump_smbus_registers();
191 sdram_initialize(nodes, ctrl);