5 #define QRANK_DIMM_SUPPORT 1
7 #if CONFIG_LOGICAL_CPUS==1
8 #define SET_NB_CFG_54 1
13 #include <device/pci_def.h>
15 #include <device/pnp_def.h>
16 #include <arch/romcc_io.h>
17 #include <cpu/x86/lapic.h>
18 #include "option_table.h"
19 #include "pc80/mc146818rtc_early.c"
20 #include "pc80/serial.c"
21 #include "arch/i386/lib/console.c"
22 #include "lib/ramtest.c"
24 #include <cpu/amd/model_fxx_rev.h>
26 #include "northbridge/amd/amdk8/incoherent_ht.c"
27 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
28 #include "northbridge/amd/amdk8/raminit.h"
29 #include "cpu/amd/model_fxx/apic_timer.c"
30 #include "lib/delay.c"
31 #include "cpu/x86/lapic/boot_cpu.c"
32 #include "northbridge/amd/amdk8/reset_test.c"
33 #include "northbridge/amd/amdk8/debug.c"
34 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
36 #include "cpu/amd/mtrr/amd_earlymtrr.c"
37 #include "cpu/x86/bist.h"
39 #include "northbridge/amd/amdk8/setup_resource_map.c"
41 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
43 static void memreset_setup(void)
47 static void memreset(int controllers, const struct mem_controller *ctrl)
51 static inline void activate_spd_rom(const struct mem_controller *ctrl)
56 static inline int spd_read_byte(unsigned device, unsigned address)
58 return smbus_read_byte(device, address);
61 #include "northbridge/amd/amdk8/raminit.c"
62 #include "northbridge/amd/amdk8/coherent_ht.c"
63 #include "lib/generic_sdram.c"
65 /* tyan does not want the default */
66 #include "resourcemap.c"
68 #include "cpu/amd/dualcore/dualcore.c"
71 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
72 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
74 #include "cpu/amd/car/copy_and_run.c"
76 #include "cpu/amd/car/post_cache_as_ram.c"
78 #include "cpu/amd/model_fxx/init_cpus.c"
80 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
81 #include "northbridge/amd/amdk8/early_ht.c"
83 static void sio_setup(void)
91 byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
93 pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
95 /* LPC Positive Decode 0 */
96 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
97 /* Serial 0, Serial 1 */
98 dword |= (1<<0) | (1<<1);
99 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
102 /* s2891 has onboard LPC port 80 */
103 /*Hope I can enable port 80 here
104 It will decode port 80 to LPC, If you are using PCI post code you can not do this */
105 dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
107 pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
113 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
115 static const uint16_t spd_addr [] = {
116 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
117 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
118 #if CONFIG_MAX_PHYSICAL_CPUS > 1
119 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
120 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
125 unsigned bsp_apicid = 0;
127 struct mem_controller ctrl[8];
130 if (!((cpu_init_detectedx) || (!boot_cpu()))) {
131 /* Nothing special needs to be done to find bus 0 */
132 /* Allow the HT devices to be found */
134 enumerate_ht_chain();
138 /* Setup the ck804 */
143 bsp_apicid = init_cpus(cpu_init_detectedx);
148 w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
152 /* Halt if there was a built in self test failure */
153 report_bist_failure(bist);
155 setup_s2891_resource_map();
157 dump_pci_device(PCI_DEV(0, 0x18, 0));
158 dump_pci_device(PCI_DEV(0, 0x19, 0));
161 needs_reset = setup_coherent_ht_domain();
163 wait_all_core0_started();
164 #if CONFIG_LOGICAL_CPUS==1
165 // It is said that we should start core1 after all core0 launched
167 wait_all_other_cores_started(bsp_apicid);
170 needs_reset |= ht_setup_chains_x();
172 needs_reset |= ck804_early_setup_x();
175 printk_info("ht reset -\r\n");
179 allow_all_aps_stop(bsp_apicid);
182 //It's the time to set ctrl now;
183 fill_mem_ctrl(nodes, ctrl, spd_addr);
187 dump_spd_registers(&cpu[0]);
190 dump_smbus_registers();
194 sdram_initialize(nodes, ctrl);