src/mainboard/tyan/s2891/romstage.c

   1 //used by raminit
   2 #define QRANK_DIMM_SUPPORT 1
   3
   4 #if CONFIG_LOGICAL_CPUS==1
   5 #define SET_NB_CFG_54 1
   6 #endif
   7
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <device/pci_def.h>
  11 #include <arch/io.h>
  12 #include <device/pnp_def.h>
  13 #include <arch/romcc_io.h>
  14 #include <cpu/x86/lapic.h>
  15 #include "option_table.h"
  16 #include "pc80/mc146818rtc_early.c"
  17 #include "pc80/serial.c"
  18 #include "console/console.c"
  19 #include "lib/ramtest.c"
  20
  21 #include <cpu/amd/model_fxx_rev.h>
  22
  23 #include "northbridge/amd/amdk8/incoherent_ht.c"
  24 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  25 #include "northbridge/amd/amdk8/raminit.h"
  26 #include "cpu/amd/model_fxx/apic_timer.c"
  27 #include "lib/delay.c"
  28 #include "cpu/x86/lapic/boot_cpu.c"
  29 #include "northbridge/amd/amdk8/reset_test.c"
  30 #include "northbridge/amd/amdk8/debug.c"
  31 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  32
  33 #include "cpu/x86/mtrr/earlymtrr.c"
  34 #include "cpu/x86/bist.h"
  35
  36 #include "northbridge/amd/amdk8/setup_resource_map.c"
  37
  38 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  39
  40 static void memreset_setup(void)
  41 {
  42 }
  43
  44 static void memreset(int controllers, const struct mem_controller *ctrl)
  45 {
  46 }
  47
  48 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  49 {
  50         /* nothing to do */
  51 }
  52
  53 static inline int spd_read_byte(unsigned device, unsigned address)
  54 {
  55         return smbus_read_byte(device, address);
  56 }
  57
  58 #include "northbridge/amd/amdk8/raminit.c"
  59 #include "northbridge/amd/amdk8/coherent_ht.c"
  60 #include "lib/generic_sdram.c"
  61
  62  /* tyan does not want the default */
  63 #include "resourcemap.c"
  64
  65 #include "cpu/amd/dualcore/dualcore.c"
  66
  67 #define CK804_NUM 1
  68 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  69 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  70
  71
  72
  73 #include "cpu/amd/car/post_cache_as_ram.c"
  74
  75 #include "cpu/amd/model_fxx/init_cpus.c"
  76
  77 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  78 #include "northbridge/amd/amdk8/early_ht.c"
  79
  80 static void sio_setup(void)
  81 {
  82         uint32_t dword;
  83         uint8_t byte;
  84
  85         /* subject decoding*/
  86         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  87         byte |= 0x20;
  88         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  89
  90         /* LPC Positive Decode 0 */
  91         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  92         /* Serial 0, Serial 1 */
  93         dword |= (1<<0) | (1<<1);
  94         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
  95
  96 #if 1
  97         /* s2891 has onboard LPC port 80 */
  98         /*Hope I can enable port 80 here
  99         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
 100         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
 101         dword |= (1<<16);
 102         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 103 #endif
 104 }
 105
 106 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 107 {
 108         static const uint16_t spd_addr [] = {
 109                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 110                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 111 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 112                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 113                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 114 #endif
 115         };
 116
 117         int needs_reset;
 118         unsigned bsp_apicid = 0;
 119
 120         struct mem_controller ctrl[8];
 121         unsigned nodes;
 122
 123         if (!cpu_init_detectedx && boot_cpu()) {
 124                 /* Nothing special needs to be done to find bus 0 */
 125                 /* Allow the HT devices to be found */
 126
 127                 enumerate_ht_chain();
 128
 129                 sio_setup();
 130
 131                 /* Setup the ck804 */
 132                 ck804_enable_rom();
 133         }
 134
 135         if (bist == 0) {
 136                 bsp_apicid = init_cpus(cpu_init_detectedx);
 137         }
 138
 139 //      post_code(0x32);
 140
 141         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 142         uart_init();
 143         console_init();
 144
 145         /* Halt if there was a built in self test failure */
 146         report_bist_failure(bist);
 147
 148         setup_s2891_resource_map();
 149 #if 0
 150         dump_pci_device(PCI_DEV(0, 0x18, 0));
 151         dump_pci_device(PCI_DEV(0, 0x19, 0));
 152 #endif
 153
 154         needs_reset = setup_coherent_ht_domain();
 155
 156         wait_all_core0_started();
 157 #if CONFIG_LOGICAL_CPUS==1
 158         // It is said that we should start core1 after all core0 launched
 159         start_other_cores();
 160         wait_all_other_cores_started(bsp_apicid);
 161 #endif
 162
 163         needs_reset |= ht_setup_chains_x();
 164
 165         needs_reset |= ck804_early_setup_x();
 166
 167         if (needs_reset) {
 168                 printk(BIOS_INFO, "ht reset -\n");
 169                 soft_reset();
 170         }
 171
 172         allow_all_aps_stop(bsp_apicid);
 173
 174         nodes = get_nodes();
 175         //It's the time to set ctrl now;
 176         fill_mem_ctrl(nodes, ctrl, spd_addr);
 177
 178         enable_smbus();
 179 #if 0
 180         dump_spd_registers(&cpu[0]);
 181 #endif
 182 #if 0
 183         dump_smbus_registers();
 184 #endif
 185
 186         memreset_setup();
 187         sdram_initialize(nodes, ctrl);
 188
 189 #if 0
 190         print_pci_devices();
 191 #endif
 192
 193 #if 0
 194         dump_pci_devices();
 195 #endif
 196
 197         post_cache_as_ram();
 198 }
 199