src/mainboard/tyan/s2891/romstage.c

   1 #define ASSEMBLY 1
   2 #define __PRE_RAM__
   3
   4 //used by raminit
   5 #define QRANK_DIMM_SUPPORT 1
   6
   7 #if CONFIG_LOGICAL_CPUS==1
   8 #define SET_NB_CFG_54 1
   9 #endif
  10
  11 #include <stdint.h>
  12 #include <string.h>
  13 #include <device/pci_def.h>
  14 #include <arch/io.h>
  15 #include <device/pnp_def.h>
  16 #include <arch/romcc_io.h>
  17 #include <cpu/x86/lapic.h>
  18 #include "option_table.h"
  19 #include "pc80/mc146818rtc_early.c"
  20 #include "pc80/serial.c"
  21 #include "arch/i386/lib/console.c"
  22 #include "lib/ramtest.c"
  23
  24 #include <cpu/amd/model_fxx_rev.h>
  25
  26 #include "northbridge/amd/amdk8/incoherent_ht.c"
  27 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
  28 #include "northbridge/amd/amdk8/raminit.h"
  29 #include "cpu/amd/model_fxx/apic_timer.c"
  30 #include "lib/delay.c"
  31 #include "cpu/x86/lapic/boot_cpu.c"
  32 #include "northbridge/amd/amdk8/reset_test.c"
  33 #include "northbridge/amd/amdk8/debug.c"
  34 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
  35
  36 #include "cpu/amd/mtrr/amd_earlymtrr.c"
  37 #include "cpu/x86/bist.h"
  38
  39 #include "northbridge/amd/amdk8/setup_resource_map.c"
  40
  41 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
  42
  43 static void memreset_setup(void)
  44 {
  45 }
  46
  47 static void memreset(int controllers, const struct mem_controller *ctrl)
  48 {
  49 }
  50
  51 static inline void activate_spd_rom(const struct mem_controller *ctrl)
  52 {
  53         /* nothing to do */
  54 }
  55
  56 static inline int spd_read_byte(unsigned device, unsigned address)
  57 {
  58         return smbus_read_byte(device, address);
  59 }
  60
  61 #include "northbridge/amd/amdk8/raminit.c"
  62 #include "northbridge/amd/amdk8/coherent_ht.c"
  63 #include "lib/generic_sdram.c"
  64
  65  /* tyan does not want the default */
  66 #include "resourcemap.c"
  67
  68 #include "cpu/amd/dualcore/dualcore.c"
  69
  70 #define CK804_NUM 1
  71 #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
  72 #include "southbridge/nvidia/ck804/ck804_early_setup.c"
  73
  74 #include "cpu/amd/car/copy_and_run.c"
  75
  76 #include "cpu/amd/car/post_cache_as_ram.c"
  77
  78 #include "cpu/amd/model_fxx/init_cpus.c"
  79
  80 #if CONFIG_USE_FALLBACK_IMAGE == 1
  81
  82 #include "southbridge/nvidia/ck804/ck804_enable_rom.c"
  83 #include "northbridge/amd/amdk8/early_ht.c"
  84
  85 static void sio_setup(void)
  86 {
  87
  88         unsigned value;
  89         uint32_t dword;
  90         uint8_t byte;
  91
  92         /* subject decoding*/
  93         byte = pci_read_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b);
  94         byte |= 0x20;
  95         pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte);
  96
  97         /* LPC Positive Decode 0 */
  98         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0);
  99         /* Serial 0, Serial 1 */
 100         dword |= (1<<0) | (1<<1);
 101         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword);
 102
 103 #if 1
 104         /* s2891 has onboard LPC port 80 */
 105         /*Hope I can enable port 80 here
 106         It will decode port 80 to LPC, If you are using PCI post code you can not do this */
 107         dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4);
 108         dword |= (1<<16);
 109         pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword);
 110
 111 #endif
 112
 113 }
 114
 115 void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
 116 {
 117         unsigned last_boot_normal_x = last_boot_normal();
 118
 119         /* Is this a cpu only reset? or Is this a secondary cpu? */
 120         if ((cpu_init_detectedx) || (!boot_cpu())) {
 121         if (last_boot_normal_x) {
 122         goto normal_image;
 123         } else {
 124         goto fallback_image;
 125         }
 126         }
 127
 128         /* Nothing special needs to be done to find bus 0 */
 129         /* Allow the HT devices to be found */
 130
 131         enumerate_ht_chain();
 132
 133         sio_setup();
 134
 135         /* Setup the ck804 */
 136         ck804_enable_rom();
 137
 138         /* Is this a deliberate reset by the bios */
 139 //      post_code(0x22);
 140         if (bios_reset_detected() && last_boot_normal_x) {
 141         goto normal_image;
 142         }
 143         /* This is the primary cpu how should I boot? */
 144         else if (do_normal_boot()) {
 145         goto normal_image;
 146         }
 147         else {
 148         goto fallback_image;
 149         }
 150  normal_image:
 151 //      post_code(0x23);
 152         __asm__ volatile ("jmp __normal_image"
 153         : /* outputs */
 154         : "a" (bist), "b"(cpu_init_detectedx) /* inputs */
 155         );
 156
 157  fallback_image:
 158 //      post_code(0x25);
 159         ;
 160 }
 161 #endif
 162
 163 void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 164
 165 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 166 {
 167
 168 #if CONFIG_USE_FALLBACK_IMAGE == 1
 169                 failover_process(bist, cpu_init_detectedx);
 170 #endif
 171         real_main(bist, cpu_init_detectedx);
 172
 173 }
 174
 175 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 176 {
 177         static const uint16_t spd_addr [] = {
 178                 (0xa<<3)|0, (0xa<<3)|2, 0, 0,
 179                 (0xa<<3)|1, (0xa<<3)|3, 0, 0,
 180 #if CONFIG_MAX_PHYSICAL_CPUS > 1
 181                 (0xa<<3)|4, (0xa<<3)|6, 0, 0,
 182                 (0xa<<3)|5, (0xa<<3)|7, 0, 0,
 183 #endif
 184         };
 185
 186         int needs_reset;
 187         unsigned bsp_apicid = 0;
 188
 189         struct mem_controller ctrl[8];
 190         unsigned nodes;
 191
 192         if (bist == 0) {
 193                 bsp_apicid = init_cpus(cpu_init_detectedx);
 194         }
 195
 196 //      post_code(0x32);
 197
 198         w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 199         uart_init();
 200         console_init();
 201
 202         /* Halt if there was a built in self test failure */
 203         report_bist_failure(bist);
 204
 205         setup_s2891_resource_map();
 206 #if 0
 207         dump_pci_device(PCI_DEV(0, 0x18, 0));
 208         dump_pci_device(PCI_DEV(0, 0x19, 0));
 209 #endif
 210
 211         needs_reset = setup_coherent_ht_domain();
 212
 213         wait_all_core0_started();
 214 #if CONFIG_LOGICAL_CPUS==1
 215         // It is said that we should start core1 after all core0 launched
 216         start_other_cores();
 217         wait_all_other_cores_started(bsp_apicid);
 218 #endif
 219
 220         needs_reset |= ht_setup_chains_x();
 221
 222         needs_reset |= ck804_early_setup_x();
 223
 224         if (needs_reset) {
 225                 printk_info("ht reset -\r\n");
 226                 soft_reset();
 227         }
 228
 229         allow_all_aps_stop(bsp_apicid);
 230
 231         nodes = get_nodes();
 232         //It's the time to set ctrl now;
 233         fill_mem_ctrl(nodes, ctrl, spd_addr);
 234
 235         enable_smbus();
 236 #if 0
 237         dump_spd_registers(&cpu[0]);
 238 #endif
 239 #if 0
 240         dump_smbus_registers();
 241 #endif
 242
 243         memreset_setup();
 244         sdram_initialize(nodes, ctrl);
 245
 246 #if 0
 247         print_pci_devices();
 248 #endif
 249
 250 #if 0
 251         dump_pci_devices();
 252 #endif
 253
 254         post_cache_as_ram();
 255 }